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author | Piotr Pawliczek <pawliczek@chromium.org> | 2022-12-03 18:04:05 +0000 |
---|---|---|
committer | Jonathon Murphy <jpmurphy@google.com> | 2022-12-03 18:12:03 +0000 |
commit | 868032324fcc03c1e1b33a4eae619a053f688a62 (patch) | |
tree | f3414c4ed2bf2a3cdd49d7a463bcc489ac646f81 /chip | |
parent | c8325ba18b9f4d5b1f3f3bc739e83d8f591308cf (diff) | |
download | chrome-ec-868032324fcc03c1e1b33a4eae619a053f688a62.tar.gz |
Revert "ec: Support logging system boot time info"
This reverts commit c8325ba18b9f4d5b1f3f3bc739e83d8f591308cf.
Reason for revert: broke at least 9 cq builds (https://ci.chromium.org/ui/p/chromeos/builders/cq/cq-orchestrator/b8795833246203447793/overview)
Original change's description:
> ec: Support logging system boot time info
>
> This CL add support logging system boot time and hostcommand to get
> boot time info.
> EC logs elapsed time (in micro second) info since boot for different
> signal events,that can be used to calculate system boot time in cold
> boot and warm boot scenarios.
>
> Below are the events when EC logs time info
>
> ARAIL EC turns on A-RAIL
> RSMRST EC releases RSMRST#
> ESPIRST ESPIRST received
> PLTRST_LOW PLTRST# asserted
> PLTRST_HIGH PLTRST# deasserted
> EC_CUR_TIME EC current time
> cnt increments on every warm reboot and reset to 0 on
> cold reboot
>
> BUG=b:249163956
> BRANCH=none
> TEST='ectool boottime' AP console command is used to fetch data
> 'reboot' on AP console to trigger warm reboot
> 'apshutdown' on EC console to trigger cold reboot
>
> Signed-off-by: Rajesh Kumar <rajesh3.kumar@intel.com>
> Change-Id: I15fedbde252e0452270ef0e3fd4391bf624169f1
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3794612
> Reviewed-by: Boris Mittelberg <bmbm@google.com>
> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Bug: b:249163956
Change-Id: Ie83026c4a3a38c3dd24522901233f06e03430a54
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077335
Reviewed-by: Jonathon Murphy <jpmurphy@google.com>
Commit-Queue: Piotr Pawliczek <pawliczek@chromium.org>
Tested-by: Piotr Pawliczek <pawliczek@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/it83xx/espi.c | 4 | ||||
-rw-r--r-- | chip/mchp/espi.c | 9 | ||||
-rw-r--r-- | chip/npcx/espi.c | 6 |
3 files changed, 2 insertions, 17 deletions
diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c index f59f3728bf..bf52b87404 100644 --- a/chip/it83xx/espi.c +++ b/chip/it83xx/espi.c @@ -13,7 +13,6 @@ #include "power.h" #include "registers.h" #include "system.h" -#include "system_boot_time.h" #include "task.h" #include "uart.h" #include "util.h" @@ -274,7 +273,6 @@ static void espi_vw_idx7_isr(uint8_t flag_changed, uint8_t vw_evt) static void espi_chipset_reset(void) { hook_notify(HOOK_CHIPSET_RESET); - update_ap_boot_time(ESPIRST); } DECLARE_DEFERRED(espi_chipset_reset); #endif @@ -286,14 +284,12 @@ static void espi_vw_idx3_isr(uint8_t flag_changed, uint8_t vw_evt) if (pltrst) { espi_vw_host_startup(); - update_ap_boot_time(PLTRST_HIGH); } else { #ifdef CONFIG_CHIPSET_RESET_HOOK hook_call_deferred(&espi_chipset_reset_data, MSEC); #endif /* Store port 80 reset event */ port_80_write(PORT_80_EVENT_RESET); - update_ap_boot_time(PLTRST_LOW); } CPRINTS("VW PLTRST_L %sasserted", pltrst ? "de" : ""); diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c index dce81448d7..53d17e90b2 100644 --- a/chip/mchp/espi.c +++ b/chip/mchp/espi.c @@ -20,7 +20,6 @@ #include "power.h" #include "registers.h" #include "system.h" -#include "system_boot_time.h" #include "task.h" #include "tfdp_chip.h" #include "timer.h" @@ -834,7 +833,6 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal) static void espi_chipset_reset(void) { hook_notify(HOOK_CHIPSET_RESET); - update_ap_boot_time(ESPIRST); } DECLARE_DEFERRED(espi_chipset_reset); #endif @@ -869,15 +867,12 @@ void espi_vw_evt_pltrst_n(uint32_t wire_state, uint32_t bpos) { CPRINTS("VW PLTRST#: %d", wire_state); - if (wire_state) { /* Platform Reset de-assertion */ + if (wire_state) /* Platform Reset de-assertion */ espi_host_init(); - update_ap_boot_time(PLTRST_HIGH); - } else { /* assertion */ + else /* assertion */ #ifdef CONFIG_CHIPSET_RESET_HOOK hook_call_deferred(&espi_chipset_reset_data, MSEC); #endif - update_ap_boot_time(PLTRST_LOW); - } } /* OOB Reset Warn event handler */ diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c index 3bed4f4564..e73d04e988 100644 --- a/chip/npcx/espi.c +++ b/chip/npcx/espi.c @@ -13,7 +13,6 @@ #include "power.h" #include "registers.h" #include "system.h" -#include "system_boot_time.h" #include "task.h" #include "timer.h" #include "uart.h" @@ -460,14 +459,11 @@ void espi_vw_evt_pltrst(void) /* Enable eSPI peripheral channel */ SET_BIT(NPCX_ESPICFG, NPCX_ESPICFG_PCHANEN); #endif - update_ap_boot_time(PLTRST_HIGH); - } else { /* PLTRST# asserted */ #ifdef CONFIG_CHIPSET_RESET_HOOK hook_call_deferred(&espi_chipset_reset_data, MSEC); #endif - update_ap_boot_time(PLTRST_LOW); } } @@ -528,8 +524,6 @@ void espi_espirst_handler(void) /* Clear pending bit of WUI */ SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 5); - update_ap_boot_time(ESPIRST); - CPRINTS("eSPI RST issued!"); } |