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authorJun Lin <CHLin56@nuvoton.com>2022-11-17 10:41:17 +0800
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>2022-11-21 19:09:02 +0000
commit9e93cddabcdf456c3806f918739f4599596c2ce6 (patch)
treee594ecc74c1b4af3153402e2224dd81fe0c9c663 /chip
parent40170ee693204db9a8245d0874fb834766226755 (diff)
downloadchrome-ec-9e93cddabcdf456c3806f918739f4599596c2ce6.tar.gz
npcx9: fix SHA256 ROM API table address
It was found that the hardware SHA256 accelerator is broken. This is caused by the table address of SHA ROM API changed from 0x100 to 0x13C since the ES2 chip. This CL fixed the issues described above. BRANCH=none BUG=b:155771688 TEST=burn the same RW image; #define/#undef CONFIG_SHA256_HW_ACCELERATE; verify the RW hash value is the same in the console message. TEST=with the test CL:2455022, move test patterns in test/sha256.c to board/npcx9_evb/test_sha256.c; pass all test patterns. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I12ce8531a925f02474f66d90bf7efd950b3eeba3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4033807 Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Boris Mittelberg <bmbm@google.com> Tested-by: CH Lin <chlin56@nuvoton.com> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Diffstat (limited to 'chip')
-rw-r--r--chip/npcx/sha256_chip.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/npcx/sha256_chip.c b/chip/npcx/sha256_chip.c
index e2590cad65..4d90ba6e74 100644
--- a/chip/npcx/sha256_chip.c
+++ b/chip/npcx/sha256_chip.c
@@ -32,7 +32,7 @@ enum ncl_sha_type {
* The base address of the table that holds the function pointer for each
* SHA256 API in ROM.
*/
-#define NCL_SHA_BASE_ADDR 0x00000100UL
+#define NCL_SHA_BASE_ADDR 0x0000013CUL
struct ncl_sha {
/* Get the SHA context size required by SHA APIs. */
uint32_t (*get_context_size)(void);