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| author | Tinghan Shen <tinghan.shen@mediatek.com> | 2021-07-19 22:53:20 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-07-23 05:56:13 +0000 |
| commit | 8d8f5f03c59fa5dace8ff5c9c10f9579308acb2a (patch) | |
| tree | 0dfe9762aee6de09d760a3e682913af39716adfa /chip | |
| parent | b33bf2a78158c016ae952f00d9d85d690cfa3ad9 (diff) | |
| download | chrome-ec-8d8f5f03c59fa5dace8ff5c9c10f9579308acb2a.tar.gz | |
chip/mt_scp: fix 8195 IRQ default polarity
BRANCH=none
BUG=b:189300514
TEST=video_decode_accelerator_tests test-25fps.h264
Change-Id: Ia6e777fe7a349586c676b6991643676019598d7a
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3038014
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/mt_scp/mt8192/intc.h | 3 | ||||
| -rw-r--r-- | chip/mt_scp/mt8195/intc.h | 3 | ||||
| -rw-r--r-- | chip/mt_scp/rv32i_common/registers.h | 3 |
3 files changed, 6 insertions, 3 deletions
diff --git a/chip/mt_scp/mt8192/intc.h b/chip/mt_scp/mt8192/intc.h index b2035a9025..63eb1243b3 100644 --- a/chip/mt_scp/mt8192/intc.h +++ b/chip/mt_scp/mt8192/intc.h @@ -7,6 +7,9 @@ #define __CROS_EC_INTC_H /* INTC */ +#define SCP_INTC_IRQ_POL0 0xef001f20 +#define SCP_INTC_IRQ_POL1 0x0800001d +#define SCP_INTC_IRQ_POL2 0x00000020 #define SCP_INTC_GRP_LEN 3 #define SCP_INTC_IRQ_COUNT 96 diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h index f098229e8c..87181c46ca 100644 --- a/chip/mt_scp/mt8195/intc.h +++ b/chip/mt_scp/mt8195/intc.h @@ -7,6 +7,9 @@ #define __CROS_EC_INTC_H /* INTC */ +#define SCP_INTC_IRQ_POL0 0xef001f20 +#define SCP_INTC_IRQ_POL1 0x044001dd +#define SCP_INTC_IRQ_POL2 0xffffdfe0 #define SCP_INTC_IRQ_POL3 0xfffffff3 #define SCP_INTC_GRP_LEN 4 #define SCP_INTC_IRQ_COUNT 127 diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h index 82450be169..adbef5f98b 100644 --- a/chip/mt_scp/rv32i_common/registers.h +++ b/chip/mt_scp/rv32i_common/registers.h @@ -142,9 +142,6 @@ #define SCP_CORE0_WDT_CUR_VAL REG32(SCP_REG_BASE + 0x3003C) /* INTC */ -#define SCP_INTC_IRQ_POL0 0xef001f20 -#define SCP_INTC_IRQ_POL1 0x0800001d -#define SCP_INTC_IRQ_POL2 0x00000020 #define SCP_INTC_WORD(irq) ((irq) >> 5) /* word length = 2^5 */ #define SCP_INTC_BIT(irq) ((irq) & 0x1F) /* bit shift =LSB[0:4] */ #define SCP_INTC_GRP_COUNT 15 |