diff options
| author | li feng <li1.feng@intel.com> | 2015-10-30 17:36:32 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-11-04 07:09:07 -0800 |
| commit | 7e31d2650b2c5c56303dd086e53d35cd9b594a1c (patch) | |
| tree | 30e1fed68165e752e142ddcedcfd5f6f8ace6496 /chip | |
| parent | 1915367112b82a2311e4938e25aee38736af44d0 (diff) | |
| download | chrome-ec-7e31d2650b2c5c56303dd086e53d35cd9b594a1c.tar.gz | |
mec1322: reduce system stack size
Reduce system stack size from 4096 to 1024.
Increase code RAM size to 104K and reduce data RAM size
to 20K.
BUG=chrome-os-partner:45690
BRANCH=None
TEST=Tested on Kunimitsu
1. Flash EC, boot up, force to S5/G3, back to S0;
and powerd_dbus_suspend to S3, all work fine.
2. Use console command to dump system stack memory values,
the size used is around 350, >600 still available.
Change-Id: Ib004678cc16f10c94c333063b728a2816ed5b3c5
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/310581
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/mec1322/config_chip.h | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h index f81069f753..08f041f3ce 100644 --- a/chip/mec1322/config_chip.h +++ b/chip/mec1322/config_chip.h @@ -37,13 +37,12 @@ /* * The memory region for RAM is actually 0x00100000-0x00120000. - * RAM for Loader = 2k - * RAM for RO/RW = 24k - * CODE size of the Loader is 4k - * As per the above configuartion the upper 26k + * RAM for RO/RW = 20k + * CODE size of the Loader is 3k + * As per the above configuartion the upper 20k * is used to store data.The rest is for code. - * the lower 100K is flash[ 4k Loader and 96k RO/RW], - * and the higher 26K is RAM shared by loader and RO/RW. + * the lower 107K is flash[ 3k Loader and 104k RO/RW], + * and the higher 20K is RAM shared by loader and RO/RW. */ /****************************************************************************/ @@ -54,13 +53,13 @@ #define CONFIG_MEC_SRAM_SIZE (CONFIG_MEC_SRAM_BASE_END - \ CONFIG_MEC_SRAM_BASE_START) -/* 24k RAM for RO / RW / loader */ -#define CONFIG_RAM_SIZE 0x00006000 +/* 20k RAM for RO / RW / loader */ +#define CONFIG_RAM_SIZE 0x00005000 #define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - \ CONFIG_RAM_SIZE) /* System stack size */ -#define CONFIG_STACK_SIZE 4096 +#define CONFIG_STACK_SIZE 1024 /* non-standard task stack sizes */ #define IDLE_TASK_STACK_SIZE 512 |