diff options
author | Randall Spangler <rspangler@chromium.org> | 2013-12-17 13:43:17 -0800 |
---|---|---|
committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-12-19 00:12:28 +0000 |
commit | 6ab8e91658f1efc894b648cc0748af8d804915e4 (patch) | |
tree | c33da7914793452ecb37084e505230171d4eff9e /chip | |
parent | e5935f17d1798a1f19c6003e57f140446774484f (diff) | |
download | chrome-ec-6ab8e91658f1efc894b648cc0748af8d804915e4.tar.gz |
cleanup: Remove checkpatch warnings
This make minor syntactic changes and renames some camel-cased symbols
to keep checkpatch from complaining. The goal is to reduce the
temptation to use 'repo upload --no-verify'.
This is a big furball of find/replace, but no functional changes.
BUG=chromium:322144
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180495
Diffstat (limited to 'chip')
-rw-r--r-- | chip/lm4/adc_chip.h | 3 | ||||
-rw-r--r-- | chip/lm4/eeprom.c | 4 | ||||
-rw-r--r-- | chip/lm4/flash.c | 6 | ||||
-rw-r--r-- | chip/lm4/lpc.c | 8 | ||||
-rw-r--r-- | chip/lm4/peci.c | 2 | ||||
-rw-r--r-- | chip/lm4/spi.c | 12 | ||||
-rw-r--r-- | chip/mec1322/lpc.c | 2 | ||||
-rw-r--r-- | chip/stm32/flash-stm32f.c | 13 | ||||
-rw-r--r-- | chip/stm32/flash-stm32l.c | 9 | ||||
-rw-r--r-- | chip/stm32/i2c-stm32f.c | 7 | ||||
-rw-r--r-- | chip/stm32/spi.c | 4 |
11 files changed, 34 insertions, 36 deletions
diff --git a/chip/lm4/adc_chip.h b/chip/lm4/adc_chip.h index 736e6f113e..0e15d6dbd0 100644 --- a/chip/lm4/adc_chip.h +++ b/chip/lm4/adc_chip.h @@ -8,8 +8,7 @@ #ifndef __CROS_EC_ADC_CHIP_H #define __CROS_EC_ADC_CHIP_H -enum lm4_adc_sequencer -{ +enum lm4_adc_sequencer { LM4_ADC_SEQ0 = 0, LM4_ADC_SEQ1, LM4_ADC_SEQ2, diff --git a/chip/lm4/eeprom.c b/chip/lm4/eeprom.c index 6ebf82a980..b8c45c23e2 100644 --- a/chip/lm4/eeprom.c +++ b/chip/lm4/eeprom.c @@ -75,7 +75,7 @@ int eeprom_read(int block, int offset, int size, char *data) LM4_EEPROM_EEOFFSET = offset >> 2; - for ( ; size; size -= sizeof(uint32_t)) + for (; size; size -= sizeof(uint32_t)) *(d++) = LM4_EEPROM_EERDWRINC; return EC_SUCCESS; @@ -103,7 +103,7 @@ int eeprom_write(int block, int offset, int size, const char *data) LM4_EEPROM_EEOFFSET = offset >> 2; /* Write 32 bits at a time; wait for each write to complete */ - for ( ; size; size -= sizeof(uint32_t)) { + for (; size; size -= sizeof(uint32_t)) { LM4_EEPROM_EERDWRINC = *(d++); rv = wait_for_done(); diff --git a/chip/lm4/flash.c b/chip/lm4/flash.c index 62e04ec8c9..c6b676d87b 100644 --- a/chip/lm4/flash.c +++ b/chip/lm4/flash.c @@ -105,7 +105,7 @@ int flash_physical_write(int offset, int size, const char *data) i = (offset >> 2) & (FLASH_FWB_WORDS - 1); /* Copy words into buffer */ - for ( ; size > 0; size -= 4) { + for (; size > 0; size -= 4) { LM4_FLASH_FWB[i++] = *data32++; if (i == FLASH_FWB_WORDS) { rv = write_buffer(); @@ -132,8 +132,8 @@ int flash_physical_erase(int offset, int size) LM4_FLASH_FCMISC = LM4_FLASH_FCRIS; /* Clear previous error status */ - for ( ; size > 0; size -= CONFIG_FLASH_ERASE_SIZE, - offset += CONFIG_FLASH_ERASE_SIZE) { + for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE, + offset += CONFIG_FLASH_ERASE_SIZE) { int t; /* Do nothing if already erased */ diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c index 57844bd2e9..63c6e9fece 100644 --- a/chip/lm4/lpc.c +++ b/chip/lm4/lpc.c @@ -63,7 +63,7 @@ static struct host_cmd_handler_args host_cmd_args; static uint8_t host_cmd_flags; /* Flags from host command */ /* Params must be 32-bit aligned */ -static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __attribute__((aligned(4))); +static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); static int init_done; static uint8_t * const cmd_params = (uint8_t *)LPC_POOL_CMD_DATA + @@ -276,9 +276,8 @@ int lpc_keyboard_input_pending(void) void lpc_keyboard_put_char(uint8_t chr, int send_irq) { LPC_POOL_KEYBOARD[1] = chr; - if (send_irq) { + if (send_irq) keyboard_irq_assert(); - } } void lpc_keyboard_clear_buffer(void) @@ -330,7 +329,8 @@ void lpc_comx_put_char(int c) * - SMI pulse via EC_SMI_L GPIO * - SCI pulse via LPC0SCI */ -static void update_host_event_status(void) { +static void update_host_event_status(void) +{ int need_sci = 0; int need_smi = 0; diff --git a/chip/lm4/peci.c b/chip/lm4/peci.c index 052e2ddc06..44c1699d26 100644 --- a/chip/lm4/peci.c +++ b/chip/lm4/peci.c @@ -38,7 +38,7 @@ #define TEMP_AVG_LENGTH 4 /* Should be power of 2 */ static int temp_vals[TEMP_AVG_LENGTH]; -static int temp_idx = 0; +static int temp_idx; int peci_get_cpu_temp(void) { diff --git a/chip/lm4/spi.c b/chip/lm4/spi.c index 914e5f1c66..aa8785ed0e 100644 --- a/chip/lm4/spi.c +++ b/chip/lm4/spi.c @@ -25,8 +25,8 @@ int spi_enable(int enable) gpio_config_module(MODULE_SPI, 1); /* Don't use the SSI0 frame output. CS# is a GPIO so we can * keep it low during an entire transaction. */ - gpio_set_flags(GPIO_SPI_CSn, GPIO_OUTPUT); - gpio_set_level(GPIO_SPI_CSn, 1); + gpio_set_flags(GPIO_SPI_CS_L, GPIO_OUTPUT); + gpio_set_level(GPIO_SPI_CS_L, 1); /* Enable SSI port */ LM4_SSI_CR1(0) |= 0x02; @@ -35,8 +35,8 @@ int spi_enable(int enable) LM4_SSI_CR1(0) &= ~0x02; /* Make sure CS# is deselected */ - gpio_set_level(GPIO_SPI_CSn, 1); - gpio_set_flags(GPIO_SPI_CSn, GPIO_ODR_HIGH); + gpio_set_level(GPIO_SPI_CS_L, 1); + gpio_set_flags(GPIO_SPI_CS_L, GPIO_ODR_HIGH); gpio_config_module(MODULE_SPI, 0); } @@ -59,7 +59,7 @@ int spi_transaction(const uint8_t *txdata, int txlen, /* Start transaction. Need to do this explicitly because the LM4 * SSI controller pulses its frame select every byte, and the EEPROM * wants the chip select held low during the entire transaction. */ - gpio_set_level(GPIO_SPI_CSn, 0); + gpio_set_level(GPIO_SPI_CS_L, 0); while (rxcount < totallen) { /* Handle received bytes if any. We just checked rxcount < @@ -89,7 +89,7 @@ int spi_transaction(const uint8_t *txdata, int txlen, } /* End transaction */ - gpio_set_level(GPIO_SPI_CSn, 1); + gpio_set_level(GPIO_SPI_CS_L, 1); return EC_SUCCESS; } diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index 4505aaab52..fb3ace7438 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -25,7 +25,7 @@ static struct host_packet lpc_packet; static struct host_cmd_handler_args host_cmd_args; static uint8_t host_cmd_flags; /* Flags from host command */ -static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __attribute__((aligned(4))); +static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); static int init_done; static struct ec_lpc_host_args * const lpc_host_args = diff --git a/chip/stm32/flash-stm32f.c b/chip/stm32/flash-stm32f.c index c14e37044c..a49701740c 100644 --- a/chip/stm32/flash-stm32f.c +++ b/chip/stm32/flash-stm32f.c @@ -153,7 +153,7 @@ static int preserve_optb(int byte) /* The byte has been reset, no need to run preserve. */ if (*(uint16_t *)(STM32_OPTB_BASE + byte) == 0xffff) - return EC_SUCCESS;; + return EC_SUCCESS; for (i = 0; i < ARRAY_SIZE(optb); ++i) optb[i] = read_optb(i * 2); @@ -201,7 +201,7 @@ static int write_optb(int byte, uint8_t value) /* set OPTPG bit */ STM32_FLASH_CR |= OPTPG; - *hword = value ; + *hword = value; /* reset OPTPG bit */ STM32_FLASH_CR &= ~OPTPG; @@ -234,7 +234,7 @@ int flash_physical_write(int offset, int size, const char *data) /* set PG bit */ STM32_FLASH_CR |= PG; - for ( ; size > 0; size -= sizeof(uint16_t)) { + for (; size > 0; size -= sizeof(uint16_t)) { /* * Reload the watchdog timer to avoid watchdog reset when doing * long writing with interrupt disabled. @@ -242,7 +242,7 @@ int flash_physical_write(int offset, int size, const char *data) watchdog_reload(); /* wait to be ready */ - for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP) ; + for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP); i++) ; @@ -251,7 +251,7 @@ int flash_physical_write(int offset, int size, const char *data) data += 2; /* Wait for writes to complete */ - for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP) ; + for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP); i++) ; @@ -487,8 +487,7 @@ int flash_pre_init(void) prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT); need_reset = 1; } - } - else { + } else { if (prot_flags & EC_FLASH_PROTECT_RO_NOW) { /* * Write protect pin unasserted but some section is diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c index 11c22dff0c..62d20ca56e 100644 --- a/chip/stm32/flash-stm32l.c +++ b/chip/stm32/flash-stm32l.c @@ -139,8 +139,7 @@ void __attribute__((section(".iram.text"))) int i; /* Wait for ready */ - for (i = 0; (STM32_FLASH_SR & 1) && (i < flash_timeout_loop) ; - i++) + for (i = 0; (STM32_FLASH_SR & 1) && (i < flash_timeout_loop); i++) ; /* Set PROG and FPRG bits */ @@ -151,7 +150,7 @@ void __attribute__((section(".iram.text"))) *addr++ = *data++; /* Wait for writes to complete */ - for (i = 0; ((STM32_FLASH_SR & 9) != 8) && (i < flash_timeout_loop) ; + for (i = 0; ((STM32_FLASH_SR & 9) != 8) && (i < flash_timeout_loop); i++) ; @@ -205,7 +204,7 @@ int flash_physical_write(int offset, int size, const char *data) /* Wait for writes to complete */ for (i = 0; ((STM32_FLASH_SR & 9) != 8) && - (i < flash_timeout_loop) ; i++) + (i < flash_timeout_loop); i++) ; size -= sizeof(uint32_t); @@ -256,7 +255,7 @@ int flash_physical_erase(int offset, int size) /* Set PROG and ERASE bits */ STM32_FLASH_PECR |= STM32_FLASH_PECR_PROG | STM32_FLASH_PECR_ERASE; - for (address = (uint32_t *)(CONFIG_FLASH_BASE + offset) ; + for (address = (uint32_t *)(CONFIG_FLASH_BASE + offset); size > 0; size -= CONFIG_FLASH_ERASE_SIZE, address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) { timestamp_t deadline; diff --git a/chip/stm32/i2c-stm32f.c b/chip/stm32/i2c-stm32f.c index 9fba464456..2e049757e4 100644 --- a/chip/stm32/i2c-stm32f.c +++ b/chip/stm32/i2c-stm32f.c @@ -574,11 +574,12 @@ static int wait_status(int port, uint32_t mask, enum wait_t wait) r = STM32_I2C_SR1(port); while (mask ? ((r & mask) != mask) : r) { t2 = get_time(); - if (t2.val - t1.val > I2C_TX_TIMEOUT_MASTER) { + + if (t2.val - t1.val > I2C_TX_TIMEOUT_MASTER) return EC_ERROR_TIMEOUT | (wait << 8); - } else if (t2.val - t1.val > 150) { + else if (t2.val - t1.val > 150) usleep(100); - } + r = STM32_I2C_SR1(port); } diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c index 1314e0e0d9..8e2fc6fa90 100644 --- a/chip/stm32/spi.c +++ b/chip/stm32/spi.c @@ -82,8 +82,8 @@ static const uint8_t out_preamble[4] = { * message, including protocol overhead, and must be 32-bit aligned. */ static uint8_t out_msg[SPI_MAX_RESPONSE_SIZE + sizeof(out_preamble)] - __attribute__((aligned(4))); -static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __attribute__((aligned(4))); + __aligned(4); +static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4); static uint8_t enabled; static struct host_cmd_handler_args args; static struct host_packet spi_packet; |