diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2020-07-16 11:59:18 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-07-21 13:27:40 +0000 |
| commit | 4c12a3e2d97d320f985f16703120d21c71f72d59 (patch) | |
| tree | 111d74acfe81ea50529a6701ad06688844a9381d /chip | |
| parent | 168a758cc46fcbdf52c1e8470827691ccf323f7c (diff) | |
| download | chrome-ec-4c12a3e2d97d320f985f16703120d21c71f72d59.tar.gz | |
it83xx/spi: Reset SPI module before sysjump
BUG=b:161327069
BRANCH=none
TEST=No complaining bad data from SPI continuously after sysjump.
NOTE:
We might get one bad data message after sysjump
(eg: "sysjump rw" command). Because EC isn't ready to receive
data but request from AP might be already started.
Change-Id: Ibe83c0b54c234022338a30c35b1b0564f7e5f266
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2301323
Tested-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/it83xx/registers.h | 1 | ||||
| -rw-r--r-- | chip/it83xx/spi.c | 17 |
2 files changed, 16 insertions, 2 deletions
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 3f134e8bd5..f57fedb838 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -969,6 +969,7 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_SPCTRL4 REG8(IT83XX_GCTRL_BASE+0x1C) #define IT83XX_GCTRL_MCCR3 REG8(IT83XX_GCTRL_BASE+0x20) #define IT83XX_GCTRL_SPISLVPFE BIT(6) +#define IT83XX_GCTRL_RSTC5 REG8(IT83XX_GCTRL_BASE+0x21) #define IT83XX_GCTRL_MCCR REG8(IT83XX_GCTRL_BASE+0x30) #define IT83XX_GCTRL_PMER1 REG8(IT83XX_GCTRL_BASE+0x32) #define IT83XX_GCTRL_PMER2 REG8(IT83XX_GCTRL_BASE+0x33) diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c index 2989c12bef..82f64c65c8 100644 --- a/chip/it83xx/spi.c +++ b/chip/it83xx/spi.c @@ -92,6 +92,8 @@ static void spi_bad_received_data(int count) /* State machine mismatch, timeout, or protocol we can't handle. */ spi_set_state(SPI_STATE_RX_BAD); + /* End CPU access Rx FIFO, so it can clock in bytes from AP again. */ + IT83XX_SPI_TXRXFAR = 0; CPRINTS("SPI rx bad data"); CPRINTF("in_msg=["); @@ -294,8 +296,6 @@ static void spi_init(void) /* Set FIFO data target count */ IT83XX_SPI_FTCB1R = (SPI_RX_MAX_FIFO_SIZE >> 8) & 0xff; IT83XX_SPI_FTCB0R = SPI_RX_MAX_FIFO_SIZE & 0xff; - /* SPI slave controller enable */ - IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN; #ifdef IT83XX_SPI_AUTO_RESET_RX_FIFO /* * General control register2 @@ -320,6 +320,8 @@ static void spi_init(void) spi_set_state(SPI_STATE_READY_TO_RECV); /* Interrupt status register(write one to clear) */ IT83XX_SPI_ISR = 0xff; + /* SPI slave controller enable (after settings are ready) */ + IT83XX_SPI_SPISGCR = IT83XX_SPI_SPISCEN; /* Enable SPI slave interrupt */ task_clear_pending_irq(IT83XX_IRQ_SPI_SLAVE); task_enable_irq(IT83XX_IRQ_SPI_SLAVE); @@ -329,6 +331,17 @@ static void spi_init(void) } DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI); +/* reset slave SPI module */ +static void spi_reset(void) +{ + /* + * Reset SPI module before sysjump. New FW images (RO/RW) will + * re-configure it. + */ + IT83XX_GCTRL_RSTC5 |= BIT(1); +} +DECLARE_HOOK(HOOK_SYSJUMP, spi_reset, HOOK_PRIO_DEFAULT); + /* Get protocol information */ enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args) { |