diff options
| author | Randall Spangler <rspangler@chromium.org> | 2013-11-15 16:59:10 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-11-19 18:30:16 +0000 |
| commit | af2c11e3e39621bc5677b4996fcbbe0e0afe224f (patch) | |
| tree | 892db2cd0013f973a9c27209ce38089f03a15c87 /chip | |
| parent | 082d8b2e2d992b12a5eded68ce7723c85e7b9318 (diff) | |
| download | chrome-ec-af2c11e3e39621bc5677b4996fcbbe0e0afe224f.tar.gz | |
stm32: Flush UART buffer before changing EC core clock speed
Otherwise UART output gets garbled because there's a delay between
changing core clock and the UART divider. Fortunately, the glitch is
cosmetic and doesn't affect proper EC operation.
BUG=chrome-os-partner:23982
BRANCH=none
TEST=power on, power off on pit or nyan --> no UART glitch
Change-Id: I32bef119b850a340fc616b83a4b088b20f17267f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177087
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Tested-by: Yung-chieh Lo <yjlou@chromium.org>
Commit-Queue: Yung-chieh Lo <yjlou@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/clock-stm32l.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c index 3cb09f69bf..b2de4e8073 100644 --- a/chip/stm32/clock-stm32l.c +++ b/chip/stm32/clock-stm32l.c @@ -148,8 +148,14 @@ void clock_enable_module(enum module_id module, int enable) new_mask = clock_mask & ~(1 << module); /* Only change clock if needed */ - if ((!!new_mask) != (!!clock_mask)) + if ((!!new_mask) != (!!clock_mask)) { + + /* Flush UART before switching clock speed */ + cflush(); + clock_set_osc(new_mask ? OSC_HSI : OSC_MSI); + } + clock_mask = new_mask; } |