gpio: add gpio flags to disable sleep

Add GPIO_SLEEP_DIS_LOW and GPIO_SLEEP_DIS_HIGH to disable sleep when a
gpio with one of those flags is asserted.

GPIO_SLEEP_DIS_LOW disables sleep when the signal is set to 0.
GPIO_SLEEP_DIS_HIGH disables sleep when the signal is set to 1.

This will disable all forms of sleep. The flags can be used for ccd
signals to ensure cr50 doesn't enter sleep while c2d2 or servo micro are
relying on a ccd signal to flash the device.

These flags should not be add to signals used during normal cr50
operation. They disable regular sleep regular sleep so using them will
significantly increase cr50 power consumption.

This change adds GPIO_SLEEP_DIS_HIGH to AP_FLASH_SELECT. I'll add more
signals in followup CLs.

This change also replaces SLEEP_MASK_CHARGING with SLEEP_MASK_GPIO.
Nothing was using SLEEP_MASK_CHARGING.

BUG=b:229974371
TEST=Toggle AP_FLASH_SELECT while the AP is off. Verify cr50 doesn't
enter deep sleep and the gpiocfg and sleepmask output looks ok.

	> gpioset AP_FLASH_SELECT 1
	> gpiocfg
	GPIO0_GPIO1:    read 0 drive 0
	GPIO0_GPIO2:    read 1 drive 1
	GPIO1_GPIO0:    read 0 INT_RISING
	GPIO1_GPIO1:    read 0 INT_HIGH
	GPIO1_GPIO4:    read 0 INT_FALLING
	GPIO1_GPIO5:    read 0 drive 1
	GPIO1_GPIO7:    read 0 INT_RISING
	GPIO1_GPIO8:    read 0 INT_FALLING

	gpio sleepmask: 00001000
	> sleepmask
	sleep mask: 00000008
	> gpioset AP_FLASH_SELECT 0
	> gpiocfg
	GPIO0_GPIO1:    read 0 drive 0
	GPIO0_GPIO2:    read 0 drive 0
	GPIO1_GPIO0:    read 0 INT_RISING
	GPIO1_GPIO1:    read 0 INT_HIGH
	GPIO1_GPIO4:    read 0 INT_FALLING
	GPIO1_GPIO5:    read 0 drive 1
	GPIO1_GPIO7:    read 0 INT_RISING
	GPIO1_GPIO8:    read 0 INT_FALLING

	gpio sleepmask: 00000000
	> sleepmask
	sleep mask: 00000000
	>

Change-Id: I1de35455c5a6702635fb714b14d6791f8e5eb2ed
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3605881
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>

1 files changed, 44 insertions, 0 deletions

diff --git a/chip/g/gpio.c b/chip/g/gpio.c
index 3704d1b1bf..b37588453f 100644
--- a/chip/g/gpio.c
+++ b/chip/g/gpio.c
@@ -8,6 +8,7 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "registers.h"
+#include "system.h"
 #include "task.h"
 
 /*
@@ -35,10 +36,51 @@ static void set_one_gpio_bit(uint32_t port, uint16_t mask, int value)
 		GR_GPIO_MASKHIGHBYTE(port, mask >> 8) = value ? mask : 0;
 }
 
+static uint32_t gpio_sleepmask;
+
+static void gpio_control_sleep(enum gpio_signal signal, int enable)
+{
+#ifdef CONFIG_GPIO_DISABLE_SLEEP
+	uint32_t signal_mask;
+
+	/* There are only 32 gpios, so this shouldn't be possible. */
+	if (signal > 31)
+		return;
+
+	signal_mask = BIT(signal);
+
+	if (enable) {
+		gpio_sleepmask |= signal_mask;
+		disable_sleep(SLEEP_MASK_GPIO);
+		return;
+	}
+	if (!(gpio_sleepmask & signal_mask))
+		return;
+
+	gpio_sleepmask &= ~signal_mask;
+	if (gpio_sleepmask)
+		return;
+
+	/* The last gpio disabling sleep was deasserted. Reenable sleep. */
+	enable_sleep(SLEEP_MASK_GPIO);
+	/*
+	 * Give extra time for activity to finish up. These signals are rarely
+	 * asserted, so 10 seconds won't affect normal activity.
+	 */
+	delay_sleep_by(10 * SECOND);
+#endif /* CONFIG_GPIO_DISABLE_SLEEP */
+}
+
 void gpio_set_level(enum gpio_signal signal, int value)
 {
 	const struct gpio_info *g = gpio_list + signal;
 
+	if (g->flags & GPIO_OUTPUT) {
+		if (g->flags & GPIO_SLEEP_DIS_HIGH)
+			gpio_control_sleep(signal, value);
+		else if (g->flags & GPIO_SLEEP_DIS_LOW)
+			gpio_control_sleep(signal, !value);
+	}
 	if (g->flags & GPIO_OPEN_DRAIN) {
 		if (value) {
 			GR_GPIO_CLRDOUTEN(g->port) = g->mask;
@@ -614,6 +656,8 @@ static int command_gpiocfg(int argc, char **argv)
 	show_gpiocfg(0);
 	show_gpiocfg(1);
 
+	ccprintf("\ngpio sleepmask: %08x\n", gpio_sleepmask);
+
 	return EC_SUCCESS;
 }
 DECLARE_SAFE_CONSOLE_COMMAND(gpiocfg, command_gpiocfg,