diff options
| author | Bill Richardson <wfrichar@chromium.org> | 2016-08-29 17:01:49 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-09-09 00:04:48 -0700 |
| commit | b9a55a09ecc891131444f1df422306357005fa0c (patch) | |
| tree | c0f0a494bf0771cd85f1df6feaeb9dbd54a14167 /chip | |
| parent | 60fc54854cffea213933cccd223ad80770cb5fb3 (diff) | |
| download | chrome-ec-b9a55a09ecc891131444f1df422306357005fa0c.tar.gz | |
g: override RBOX fuses for correct POR behavior
Sanity tested by powering up cr50 and checking for correct RBOX
register values.
This patch is mainly to address RBOX debounce issues and key blocking
while EC_RST is asserted. A debounce value less than 4, sometimes
causes initial pin values to be incorrectly detected. The latter is
related to https://chromium-review.googlesource.com/#/c/357590/.
As RBOX controls cannot be selectively bypassed (they have to be
bypassed as a group), all registers are set up in this patch
BUG=chrome-os-partner:54602
BRANCH=None
CQ-DEPEND=CL:377621
TEST=manual on Kevin
Do three-finger salute, enter recovery mode.
Change-Id: Ieb82c94fa33888ead359a77bf77981567998b3fc
Signed-off-by: Timothy Chen <timothytim@google.com>
Reviewed-on: https://chromium-review.googlesource.com/372001
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/g/rbox.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/chip/g/rbox.c b/chip/g/rbox.c index 85f83d33ce..627c587563 100644 --- a/chip/g/rbox.c +++ b/chip/g/rbox.c @@ -28,5 +28,51 @@ static void rbox_init(void) /* Clear any wakeup bits (write 0x2, then 0x0) */ GREG32(RBOX, WAKEUP) = GC_RBOX_WAKEUP_CLEAR_MASK; GREG32(RBOX, WAKEUP) = 0; + + /* Override rbox fuses and setup correct behavior */ + GWRITE(RBOX, DEBUG_CLK10HZ_COUNT, 0x63ff); + GWRITE(RBOX, DEBUG_SHORT_DELAY_COUNT, 0x4ff); + GWRITE(RBOX, DEBUG_LONG_DELAY_COUNT, 0x31); + GWRITE(RBOX, DEBUG_DEBOUNCE, 0x4); + GWRITE(RBOX, DEBUG_KEY_COMBO0, 0xC0); + GWRITE(RBOX, DEBUG_KEY_COMBO1, 0x0); + GWRITE(RBOX, DEBUG_KEY_COMBO2, 0x0); + /* DEBUG_BLOCK_OUTPUT value should be 0x7 */ + GWRITE(RBOX, DEBUG_BLOCK_OUTPUT, + GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_MASK | + GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_MASK | + GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_MASK); + /* DEBUG_POL value should be 0x21 */ + GWRITE(RBOX, DEBUG_POL, + 0x1 << GC_RBOX_DEBUG_POL_AC_PRESENT_LSB | + 0x0 << GC_RBOX_DEBUG_POL_PWRB_IN_LSB | + 0x0 << GC_RBOX_DEBUG_POL_PWRB_OUT_LSB | + 0x0 << GC_RBOX_DEBUG_POL_KEY0_IN_LSB | + 0x0 << GC_RBOX_DEBUG_POL_KEY0_OUT_LSB | + 0x1 << GC_RBOX_DEBUG_POL_KEY1_IN_LSB | + 0x0 << GC_RBOX_DEBUG_POL_KEY1_OUT_LSB | + 0x0 << GC_RBOX_DEBUG_POL_EC_RST_LSB | + 0x0 << GC_RBOX_DEBUG_POL_BATT_DISABLE_LSB); + /* DEBUG_TERM value should be 0x1204 */ + GWRITE(RBOX, DEBUG_TERM, + 0x0 << GC_RBOX_DEBUG_TERM_AC_PRESENT_LSB | + 0x1 << GC_RBOX_DEBUG_TERM_ENTERING_RW_LSB | + 0x0 << GC_RBOX_DEBUG_TERM_PWRB_IN_LSB | + 0x0 << GC_RBOX_DEBUG_TERM_PWRB_OUT_LSB | + 0x2 << GC_RBOX_DEBUG_TERM_KEY0_IN_LSB | + 0x0 << GC_RBOX_DEBUG_TERM_KEY0_OUT_LSB | + 0x1 << GC_RBOX_DEBUG_TERM_KEY1_IN_LSB | + 0x0 << GC_RBOX_DEBUG_TERM_KEY1_IN_LSB); + /* DEBUG_BLOCK_OUTPUT value should be 0x157 */ + GWRITE(RBOX, DEBUG_DRIVE, + 0x3 << GC_RBOX_DEBUG_DRIVE_PWRB_OUT_LSB | + 0x1 << GC_RBOX_DEBUG_DRIVE_KEY0_OUT_LSB | + 0x1 << GC_RBOX_DEBUG_DRIVE_KEY1_OUT_LSB | + 0x1 << GC_RBOX_DEBUG_DRIVE_EC_RST_LSB | + 0x1 << GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_LSB); + /* FUSE_CTRL value should be 0x3 */ + GWRITE(RBOX, FUSE_CTRL, + GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_MASK | + GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_MASK); } DECLARE_HOOK(HOOK_INIT, rbox_init, HOOK_PRIO_DEFAULT - 1); |