diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2021-09-01 14:14:23 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-09-02 20:03:32 +0000 |
| commit | b7acae8fb5137f76494ca32c7786e6f4630195b2 (patch) | |
| tree | ffffbe86f1b96611afe613a2b3d0b61c93edf8ce /chip | |
| parent | 92229de1df4976c93654709fdc164525356b266d (diff) | |
| download | chrome-ec-b7acae8fb5137f76494ca32c7786e6f4630195b2.tar.gz | |
it83xx/nds32: Ensure EXT_IER has been disabled before enabling CPU interrupt
This CL read (load operation) an EC's extended interrupt enable register
one time after configured. The load operation will ensure chip-level's
interrupt has been disabled before enabling CPU interrupt.
This CL will also assert failure if EC get interrupt number 0 in ISR.
BRANCH=dedede
BUG=b:197308582
TEST=No system reboot on storo during the drop test.
Change-Id: I593d78626d1e3bb92e5316d1ff78f0ee54711741
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124483
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/it83xx/gpio.c | 3 | ||||
| -rw-r--r-- | chip/it83xx/irq.c | 10 |
2 files changed, 12 insertions, 1 deletions
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c index f15adb431a..e6043267fd 100644 --- a/chip/it83xx/gpio.c +++ b/chip/it83xx/gpio.c @@ -871,6 +871,9 @@ static void __gpio_irq(void) /* Determine interrupt number. */ int irq = intc_get_ec_int(); + /* assert failure if interrupt number is zero */ + ASSERT(irq); + #ifdef HAS_TASK_KEYSCAN if (irq == IT83XX_IRQ_WKINTC) { keyboard_raw_interrupt(); diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c index 308fa5b2e7..fb01309721 100644 --- a/chip/it83xx/irq.c +++ b/chip/it83xx/irq.c @@ -134,8 +134,16 @@ void chip_disable_irq(int irq) } /* SOC's interrupts use CPU HW interrupt 2 ~ 15 */ - if (IS_ENABLED(CHIP_CORE_NDS32)) + if (IS_ENABLED(CHIP_CORE_NDS32)) { + volatile uint8_t _ext_ier __unused; + IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) &= ~BIT(bit); + /* + * This load operation will guarantee the above modification of + * EC's register can be seen by any following instructions. + */ + _ext_ier = IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)); + } } void chip_clear_pending_irq(int irq) |