it83xx: read_clear_int_mask() read and clear interrupt bit.

This change pulled the operation of interrupt disable into
read_clear_int_mask().
Because riscv core supports instruction csrrc to atomic read and
clear bit in CSR register. With this change, we won't need to separate
operations of reading and clearing interrupt bit on riscv core.

BUG=none
BRANCH=none
TEST=read_clear_int_mask() is able to disable interrupt and return
     saved interrupt bit on both nds32 and riscv cores.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I871aab747b950b7948cdeb7911fcf8c09d55df5d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2419739
Reviewed-by: Jett Rink <jettrink@chromium.org>

5 files changed, 11 insertions, 17 deletions

diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
index fe657438c4..be02a8f813 100644
--- a/chip/it83xx/ec2i.c
+++ b/chip/it83xx/ec2i.c
@@ -245,10 +245,9 @@ static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel)
 enum ec2i_message ec2i_read(enum host_pnpcfg_index index)
 {
 	enum ec2i_message ret = EC2I_READ_ERROR;
-	uint32_t int_mask = get_int_mask();
-
 	/* critical section with interrupts off */
-	interrupt_disable();
+	uint32_t int_mask = read_clear_int_mask();
+
 	/* Set index */
 	if (ec2i_write_pnpcfg(EC2I_ACCESS_INDEX, index) == EC2I_WRITE_SUCCESS)
 		/* read data port */
@@ -263,10 +262,9 @@ enum ec2i_message ec2i_read(enum host_pnpcfg_index index)
 enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data)
 {
 	enum ec2i_message ret = EC2I_WRITE_ERROR;
-	uint32_t int_mask = get_int_mask();
-
 	/* critical section with interrupts off */
-	interrupt_disable();
+	uint32_t int_mask = read_clear_int_mask();
+
 	/* Set index */
 	if (ec2i_write_pnpcfg(EC2I_ACCESS_INDEX, index) == EC2I_WRITE_SUCCESS)
 		/* Set data */
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
index 49c3dea103..3dd6d16268 100644
--- a/chip/it83xx/gpio.c
+++ b/chip/it83xx/gpio.c
@@ -442,10 +442,9 @@ test_mockable int gpio_get_level(enum gpio_signal signal)
 
 void gpio_set_level(enum gpio_signal signal, int value)
 {
-	uint32_t int_mask = get_int_mask();
-
 	/* critical section with interrupts off */
-	interrupt_disable();
+	uint32_t int_mask = read_clear_int_mask();
+
 	if (value)
 		IT83XX_GPIO_DATA(gpio_list[signal].port) |=
 				 gpio_list[signal].mask;
diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c
index 1fc90ebe67..291751a1cb 100644
--- a/chip/it83xx/hwtimer.c
+++ b/chip/it83xx/hwtimer.c
@@ -228,10 +228,9 @@ DECLARE_IRQ(CPU_INT_GROUP_3, __hw_clock_source_irq, 1);
 #define CYCLES_125NS (125*(PLL_CLOCK/SECOND) / 1000)
 uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer)
 {
-	uint32_t prev_mask = get_int_mask();
+	uint32_t prev_mask = read_clear_int_mask();
 	uint32_t val;
 
-	interrupt_disable();
 	asm volatile(
 		/* read observation register for the first time */
 		"lwi %0,[%1]\n\t"
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
index 0431019101..ae66181430 100644
--- a/chip/it83xx/lpc.c
+++ b/chip/it83xx/lpc.c
@@ -337,8 +337,8 @@ void lpc_keyboard_put_char(uint8_t chr, int send_irq)
 
 void lpc_keyboard_clear_buffer(void)
 {
-	uint32_t int_mask = get_int_mask();
-	interrupt_disable();
+	uint32_t int_mask = read_clear_int_mask();
+
 	/* bit6, write-1 clear OBF */
 	IT83XX_KBC_KBHICR |= BIT(6);
 	IT83XX_KBC_KBHICR &= ~BIT(6);
diff --git a/chip/mt8192_scp/ipi.c b/chip/mt8192_scp/ipi.c
index 83d9fa8ebb..4081e47075 100644
--- a/chip/mt8192_scp/ipi.c
+++ b/chip/mt8192_scp/ipi.c
@@ -30,10 +30,8 @@ static uint32_t disable_irq_count, saved_int_mask;
 
 void ipi_disable_irq(void)
 {
-	if (atomic_inc(&disable_irq_count, 1) == 0) {
-		saved_int_mask = get_int_mask();
-		interrupt_disable();
-	}
+	if (atomic_inc(&disable_irq_count, 1) == 0)
+		saved_int_mask = read_clear_int_mask();
 }
 
 void ipi_enable_irq(void)