diff options
| author | Scott Collyer <scollyer@google.com> | 2020-04-15 12:03:05 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-07-29 03:49:15 +0000 |
| commit | a78ca7b158c4ca6c33086b84b929a1c8385d8d09 (patch) | |
| tree | 8735559776193957b8a6060777c239ee1e49d90d /chip | |
| parent | 4213a3086f09ee74b1fc1306ef679ca8676ffaba (diff) | |
| download | chrome-ec-a78ca7b158c4ca6c33086b84b929a1c8385d8d09.tar.gz | |
stm32g4: Add gpio support
This CL adds stm32g4 chip specific changes. Most of gpio code can be
reused as is. This file enables clocks and IRQs for supported GPIO
banks. This was based on F4 family as the reference.
BUG=b:148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I47d0b08675b53597b5a0e938d576682e63cc59e0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195546
Tested-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/gpio-stm32g4.c | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/chip/stm32/gpio-stm32g4.c b/chip/stm32/gpio-stm32g4.c new file mode 100644 index 0000000000..55b2c11e7b --- /dev/null +++ b/chip/stm32/gpio-stm32g4.c @@ -0,0 +1,66 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* GPIO module for Chrome EC */ + +#include "clock.h" +#include "common.h" +#include "gpio.h" +#include "hooks.h" +#include "registers.h" +#include "task.h" +#include "util.h" + +int gpio_required_clocks(void) +{ + const int gpio_ports_used = (0 +# define GPIO(name, pin, flags) pin +# define GPIO_INT(name, pin, flags, signal) pin +# define ALTERNATE(pinmask, function, module, flagz) pinmask +# define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT ## port +# define PIN_MASK(port, mask) PIN(port, 0) +# include "gpio.wrap" + ); + + /* + * If no ports are in use, then system_is_reboot_warm + * may not be valid. + */ + ASSERT(gpio_ports_used); + + return gpio_ports_used; +} + +void gpio_enable_clocks(void) +{ + /* Enable only ports that are referenced in the gpio.inc */ + STM32_RCC_AHB2ENR |= gpio_required_clocks(); + + /* Delay 1 AHB clock cycle after the clock is enabled */ + clock_wait_bus_cycles(BUS_AHB, 1); +} + +static void gpio_init(void) +{ + /* Enable IRQs now that pins are set up */ + task_enable_irq(STM32_IRQ_EXTI0); + task_enable_irq(STM32_IRQ_EXTI1); + task_enable_irq(STM32_IRQ_EXTI2); + task_enable_irq(STM32_IRQ_EXTI3); + task_enable_irq(STM32_IRQ_EXTI4); + task_enable_irq(STM32_IRQ_EXTI9_5); + task_enable_irq(STM32_IRQ_EXTI15_10); +} +DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); + +DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1); +DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1); + +#include "gpio-f0-l.c" |