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authorMarius Schilder <mschilder@google.com>2018-03-26 19:11:35 -0700
committerchrome-bot <chrome-bot@chromium.org>2018-03-27 20:34:41 -0700
commite23e0cf3c002a7ed40a6334b5e5141815691c612 (patch)
treea51159332955d50b8e1b1cb9d0c5d3443b3076b1 /chip
parentda431a78985da7a1ff474aa8d960cf5d7ad1f88d (diff)
downloadchrome-ec-e23e0cf3c002a7ed40a6334b5e5141815691c612.tar.gz
g: add missing define for UART register UART_VAL.
Holds most recent 16 oversampled values of rx and cts inputs. Signed-off-by: mschilder@google.com TEST=buildall -j8 BUG=None BRANCH=None Change-Id: I798b8c2ba645712600d7634769f418d81dec5f79 Reviewed-on: https://chromium-review.googlesource.com/981775 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Diffstat (limited to 'chip')
-rw-r--r--chip/g/registers.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/chip/g/registers.h b/chip/g/registers.h
index de80896b70..9c16df7f62 100644
--- a/chip/g/registers.h
+++ b/chip/g/registers.h
@@ -166,6 +166,7 @@ static inline int x_uart_addr(int ch, int offset)
#define GR_UART_ISTATECLR(ch) X_UARTREG(ch, GC_UART_ISTATECLR_OFFSET)
#define GR_UART_FIFO(ch) X_UARTREG(ch, GC_UART_FIFO_OFFSET)
#define GR_UART_RFIFO(ch) X_UARTREG(ch, GC_UART_RFIFO_OFFSET)
+#define GR_UART_VAL(ch) X_UARTREG(ch, GC_UART_VAL_OFFSET)
/*
* Our ARM core doesn't have GPIO alternate functions, but it does have a full