diff options
author | Bill Richardson <wfrichar@chromium.org> | 2015-07-09 13:42:52 -0700 |
---|---|---|
committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-13 18:43:50 +0000 |
commit | 41b538d4c6df5311fbf76495c187a4781938ae49 (patch) | |
tree | 23274def05ff1a3e7a8d8bd9bc447538ad6645e8 /chip | |
parent | 4c708232ac82e2c0bfe075027fbe88afd9456535 (diff) | |
download | chrome-ec-41b538d4c6df5311fbf76495c187a4781938ae49.tar.gz |
Cr50: Pass SPI and SPS modes to sps_register_rx_handler()
This lets the RX interrupt handler configure the wire protocol
(clock polarity and phase) and SPS communication mode that it
would prefer.
BUG=chrome-os-partner:40969
BRANCH=none
TEST=make buildall
This is just a refactoring, since the sps_hc.c module is the only
thing that uses this (in one mode only). I tested it using
extra/ftdi_hostcmd and it still works.
Change-Id: I9ed26e9fa66de65e72f188184f4f3f41a5b5562a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284922
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/g/sps.c | 33 | ||||
-rw-r--r-- | chip/g/sps.h | 21 | ||||
-rw-r--r-- | chip/g/sps_hc.c | 3 |
3 files changed, 36 insertions, 21 deletions
diff --git a/chip/g/sps.c b/chip/g/sps.c index c68e3b0c60..5e8f1ffc2e 100644 --- a/chip/g/sps.c +++ b/chip/g/sps.c @@ -11,14 +11,6 @@ #include "sps.h" #include "task.h" -/* SPS Control Mode */ -enum sps_mode { - SPS_GENERIC_MODE = 0, - SPS_SWETLAND_MODE = 1, - SPS_ROM_MODE = 2, - SPS_UNDEF_MODE = 3, -}; - /* * Hardware pointers use one extra bit to indicate wrap around. This means we * can fill the FIFO completely, but it also means that the FIFO index and the @@ -127,18 +119,16 @@ int sps_transmit(uint8_t *data, size_t data_size) /* * Disable interrupts, clear and reset the HW FIFOs. */ -static void sps_reset(void) -{ - enum sps_mode mode = SPS_GENERIC_MODE; - enum spi_clock_mode clk_mode = SPI_CLOCK_MODE0; +static void sps_reset(enum spi_clock_mode m_spi, enum sps_mode m_sps) +{ /* Disable All Interrupts */ GREG32(SPS, ICTRL) = 0; - GWRITE_FIELD(SPS, CTRL, MODE, mode); + GWRITE_FIELD(SPS, CTRL, MODE, m_sps); GWRITE_FIELD(SPS, CTRL, IDLE_LVL, 0); - GWRITE_FIELD(SPS, CTRL, CPHA, clk_mode & 1); - GWRITE_FIELD(SPS, CTRL, CPOL, (clk_mode >> 1) & 1); + GWRITE_FIELD(SPS, CTRL, CPHA, m_spi & 1); + GWRITE_FIELD(SPS, CTRL, CPOL, (m_spi >> 1) & 1); GWRITE_FIELD(SPS, CTRL, TXBITOR, 1); /* MSB first */ GWRITE_FIELD(SPS, CTRL, RXBITOR, 1); /* MSB first */ @@ -260,13 +250,20 @@ void sps_unregister_rx_handler(void) { task_disable_irq(GC_IRQNUM_SPS0_RXFIFO_LVL_INTR); task_disable_irq(GC_IRQNUM_SPS0_CS_DEASSERT_INTR); - sps_reset(); sps_rx_handler = NULL; + + /* The modes don't really matter since we're disabling interrupts. + * Mostly we just want to reset the FIFOs. */ + sps_reset(SPI_CLOCK_MODE0, SPS_GENERIC_MODE); } -void sps_register_rx_handler(rx_handler_fn func) +void sps_register_rx_handler(enum spi_clock_mode m_spi, + enum sps_mode m_sps, + rx_handler_fn func) { - sps_unregister_rx_handler(); + task_disable_irq(GC_IRQNUM_SPS0_RXFIFO_LVL_INTR); + task_disable_irq(GC_IRQNUM_SPS0_CS_DEASSERT_INTR); + sps_reset(m_spi, m_sps); sps_rx_handler = func; sps_enable(); task_enable_irq(GC_IRQNUM_SPS0_RXFIFO_LVL_INTR); diff --git a/chip/g/sps.h b/chip/g/sps.h index f92d083ae8..c4c96d77df 100644 --- a/chip/g/sps.h +++ b/chip/g/sps.h @@ -16,6 +16,15 @@ #include <stdint.h> #include <stddef.h> +#include "spi.h" + +/* SPS Control Mode */ +enum sps_mode { + SPS_GENERIC_MODE = 0, + SPS_SWETLAND_MODE = 1, + SPS_ROM_MODE = 2, + SPS_UNDEF_MODE = 3, +}; /** * Every RX byte simultaneously sends a TX byte, no matter what. This @@ -44,16 +53,24 @@ int sps_transmit(uint8_t *data, size_t data_size); * * The handler is also called when the chip select deasserts, in case any * cleanup is required. + * + * @param data Pointer to the incoming data, in its buffer + * @param data_size Number of new bytes visible without wrapping + * @param cs_enabled True if the chip select is still enabled */ -typedef void (*rx_handler_fn)(uint8_t *data, size_t data_size, int cs_status); +typedef void (*rx_handler_fn)(uint8_t *data, size_t data_size, int cs_enabled); /** * Register the RX handler function. This will reset and disable the RX FIFO, * replace any previous handler, then enable the RX FIFO. * + * @param m_spi SPI clock polarity and phase + * @param m_sps SPS interface protocol * @param func RX handler function */ -void sps_register_rx_handler(rx_handler_fn func); +void sps_register_rx_handler(enum spi_clock_mode m_spi, + enum sps_mode m_sps, + rx_handler_fn func); /** * Unregister the RX handler. This will reset and disable the RX FIFO. diff --git a/chip/g/sps_hc.c b/chip/g/sps_hc.c index e3eb043018..f54df356f9 100644 --- a/chip/g/sps_hc.c +++ b/chip/g/sps_hc.c @@ -254,7 +254,8 @@ static void sps_hc_enable(void) state = SPI_STATE_DISABLED; /* Ready to receive */ - sps_register_rx_handler(hc_rx_handler); + sps_register_rx_handler(SPI_CLOCK_MODE0, SPS_GENERIC_MODE, + hc_rx_handler); /* Here we go */ discard_response = 0; |