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authorFurquan Shaikh <furquan@google.com>2018-09-07 11:07:05 -0700
committerchrome-bot <chrome-bot@chromium.org>2018-09-07 22:27:42 -0700
commitbd34ba0abea5246d47571eb12416b07b68b3c692 (patch)
treed769756d63ebca3fc325e3dbc91a1ffb21f41306 /chip
parent39ff41a291d16b794c98f0c371492786738f2c0a (diff)
downloadchrome-ec-bd34ba0abea5246d47571eb12416b07b68b3c692.tar.gz
npcx: Change sleep in flash_wait_ready to 10usec
flash_wait_ready had a sleep of 1 msec to check for busy bit status. This is too long of a wait for flash chip operation to complete and hence adds unnecessary delay during flash write. Changing the delay to 10usec helps cut the flash write time by 50%. This change reduces the delay to check busy bit to 10usec and also organizes the code slightly differently to use timestamp_expired() instead of decrementing timeout and checking it against 0. BUG=b:113530328 BRANCH=nocturne,grunt TEST=Verified that EC SW sync time is down to 3.4 seconds with this change. Change-Id: I5796ac3c493031c9623a9e5171ce9c5a7087089e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1213553 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r--chip/npcx/flash.c29
1 files changed, 14 insertions, 15 deletions
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c
index f1c4ce630e..d542dec674 100644
--- a/chip/npcx/flash.c
+++ b/chip/npcx/flash.c
@@ -27,8 +27,6 @@ static uint8_t flag_prot_inconsistent;
static uint8_t saved_sr1;
static uint8_t saved_sr2;
-#define FLASH_ABORT_TIMEOUT 10000
-
#ifdef CONFIG_EXTERNAL_STORAGE
#define TRISTATE_FLASH(x)
#else
@@ -79,18 +77,20 @@ static void flash_cs_level(int level)
UPDATE_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_SW_CS1, level);
}
-static int flash_wait_ready(int timeout)
+static int flash_wait_ready(void)
{
uint8_t mask = SPI_FLASH_SR1_BUSY;
-
- if (timeout <= 0)
- return EC_ERROR_INVAL;
+ const timestamp_t start = get_time();
+ const uint32_t timeout_us = 10 * SECOND;
+ const timestamp_t deadline = {
+ .val = start.val + timeout_us,
+ };
/* Chip Select down. */
flash_cs_level(0);
/* Command for Read status register */
flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY);
- while (timeout > 0) {
+ do {
/* Read status register */
NPCX_UMA_CTS = MASK_RD_1BYTE;
while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
@@ -98,14 +98,13 @@ static int flash_wait_ready(int timeout)
/* Busy bit is clear */
if ((NPCX_UMA_DB0 & mask) == 0)
break;
- if (--timeout > 0)
- msleep(1);
- }; /* Wait for Busy clear */
+ usleep(10);
+ } while (!timestamp_expired(deadline, NULL)); /* Wait for Busy clear */
/* Chip Select high. */
flash_cs_level(1);
- if (timeout == 0)
+ if (timestamp_expired(deadline, NULL))
return EC_ERROR_TIMEOUT;
return EC_SUCCESS;
@@ -116,7 +115,7 @@ static int flash_write_enable(void)
uint8_t mask = SPI_FLASH_SR1_WEL;
int rv;
/* Wait for previous operation to complete */
- rv = flash_wait_ready(FLASH_ABORT_TIMEOUT);
+ rv = flash_wait_ready();
if (rv)
return rv;
@@ -124,7 +123,7 @@ static int flash_write_enable(void)
flash_execute_cmd(CMD_WRITE_EN, MASK_CMD_ONLY);
/* Wait for flash is not busy */
- rv = flash_wait_ready(FLASH_ABORT_TIMEOUT);
+ rv = flash_wait_ready();
if (rv)
return rv;
@@ -418,7 +417,7 @@ static int flash_program_bytes(uint32_t offset, uint32_t bytes,
flash_burst_write(offset, write_size, data);
/* Wait write completed */
- rv = flash_wait_ready(FLASH_ABORT_TIMEOUT);
+ rv = flash_wait_ready();
if (rv)
return rv;
@@ -562,7 +561,7 @@ int flash_physical_erase(int offset, int size)
flash_execute_cmd(NPCX_ERASE_COMMAND, MASK_CMD_ADR);
/* Wait erase completed */
- rv = flash_wait_ready(FLASH_ABORT_TIMEOUT);
+ rv = flash_wait_ready();
if (rv)
break;
}