diff options
author | Jack Rosenthal <jrosenth@chromium.org> | 2019-04-26 14:40:09 -0600 |
---|---|---|
committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2019-05-07 21:32:38 +0000 |
commit | 103d87a2e8d20ea77c68b6d2fd08f8b216380efc (patch) | |
tree | 56fbae4cf4b947c33316d13de230350730f4b2f1 /chip | |
parent | 95945aaf61d9576d72bd6931b3cef3411cc657ac (diff) | |
download | chrome-ec-103d87a2e8d20ea77c68b6d2fd08f8b216380efc.tar.gz |
ish: move REG32 macros for interrupt control into header files
This is a good portion of the fixes needed for b:130573158, but we
still have the HECI registers to deal with. I have those in a separate
CL as they were giving me a significant amount of trouble.
BUG=b:130573158
BRANCH=none
TEST=arcada_ish is functioning as normal after changes
Change-Id: I9c209a329d61f7f55c260006cdffbfc705521195
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1586458
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1598521
Commit-Queue: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/ish/aontaskfw/ish_aontask.c | 8 | ||||
-rw-r--r-- | chip/ish/power_mgt.c | 8 | ||||
-rw-r--r-- | chip/ish/registers.h | 66 |
3 files changed, 43 insertions, 39 deletions
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c index 374497b1ba..4bfd6fcab4 100644 --- a/chip/ish/aontaskfw/ish_aontask.c +++ b/chip/ish/aontaskfw/ish_aontask.c @@ -85,8 +85,8 @@ static void pmu_wakeup_isr(void) * Indicate completion of servicing the interrupt to IOAPIC first * then indicate completion of servicing the interrupt to LAPIC */ - REG32(IOAPIC_EOI_REG) = ISH_PMU_WAKEUP_VEC; - REG32(LAPIC_EOI_REG) = 0x0; + IOAPIC_EOI_REG = ISH_PMU_WAKEUP_VEC; + LAPIC_EOI_REG = 0x0; __asm__ volatile ("iret;"); @@ -105,8 +105,8 @@ static void reset_prep_isr(void) * Indicate completion of servicing the interrupt to IOAPIC first * then indicate completion of servicing the interrupt to LAPIC */ - REG32(IOAPIC_EOI_REG) = ISH_RESET_PREP_VEC; - REG32(LAPIC_EOI_REG) = 0x0; + IOAPIC_EOI_REG = ISH_RESET_PREP_VEC; + LAPIC_EOI_REG = 0x0; handle_reset(ISH_PM_STATE_RESET_PREP); diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c index 467d0bc55d..11b2ba3c3f 100644 --- a/chip/ish/power_mgt.c +++ b/chip/ish/power_mgt.c @@ -676,8 +676,8 @@ static void reset_prep_isr(void) * Indicate completion of servicing the interrupt to IOAPIC first * then indicate completion of servicing the interrupt to LAPIC */ - REG32(IOAPIC_EOI_REG) = ISH_RESET_PREP_VEC; - REG32(LAPIC_EOI_REG) = 0x0; + IOAPIC_EOI_REG = ISH_RESET_PREP_VEC; + LAPIC_EOI_REG = 0x0; if (pm_ctx.aon_valid) { handle_reset_in_aontask(ISH_PM_STATE_RESET_PREP); @@ -708,8 +708,8 @@ static void handle_d3(uint32_t irq_vec) * first then indicate completion of servicing the interrupt * to LAPIC */ - REG32(IOAPIC_EOI_REG) = irq_vec; - REG32(LAPIC_EOI_REG) = 0x0; + IOAPIC_EOI_REG = irq_vec; + LAPIC_EOI_REG = 0x0; pm_ctx.aon_share->pm_state = ISH_PM_STATE_D3; diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 03aac276fb..7e6b580d76 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -282,46 +282,50 @@ enum ish_i2c_port { #define CCU_SRECC_RST BIT(3) /* Used to indicate SRAM ECC reset */ /* Fabric Agent Status register */ -#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828) -#define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29) -#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28) -#define FABRIC_M_ERR_BIT BIT(24) +#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828) +#define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29) +#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28) +#define FABRIC_M_ERR_BIT BIT(24) #define FABRIC_MIA_STATUS_BIT_ERR (FABRIC_INBAND_ERR_SECONDARY_BIT | \ - FABRIC_INBAND_ERR_PRIMARY_BIT | \ - FABRIC_M_ERR_BIT) + FABRIC_INBAND_ERR_PRIMARY_BIT | \ + FABRIC_M_ERR_BIT) /* CSME Registers */ -#define ISH_RST_REG REG32(ISH_IPC_BASE + 0x44) +#define ISH_RST_REG REG32(ISH_IPC_BASE + 0x44) /* IOAPIC registers */ -#define IOAPIC_IDX 0xFEC00000 -#define IOAPIC_WDW 0xFEC00010 -#define IOAPIC_EOI_REG 0xFEC00040 - -#define IOAPIC_VERSION 0x1 -#define IOAPIC_IOREDTBL 0x10 -#define IOAPIC_REDTBL_DELMOD_FIXED 0x00000000 -#define IOAPIC_REDTBL_DESTMOD_PHYS 0x00000000 -#define IOAPIC_REDTBL_INTPOL_HIGH 0x00000000 -#define IOAPIC_REDTBL_INTPOL_LOW 0x00002000 -#define IOAPIC_REDTBL_IRR 0x00004000 -#define IOAPIC_REDTBL_TRIGGER_EDGE 0x00000000 -#define IOAPIC_REDTBL_TRIGGER_LEVEL 0x00008000 -#define IOAPIC_REDTBL_MASK 0x00010000 +#define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0) +#define IOAPIC_WDW REG32(ISH_IOAPIC_BASE + 0x10) +/* Bare address needed for assembler (ISH_IOAPIC_BASE + 0x40) */ +#define IOAPIC_EOI_REG_ADDR 0xFEC00040 +#define IOAPIC_EOI_REG REG32(IOAPIC_EOI_REG_ADDR) + +#define IOAPIC_VERSION (0x1) +#define IOAPIC_IOREDTBL (0x10) +#define IOAPIC_REDTBL_DELMOD_FIXED (0x00000000) +#define IOAPIC_REDTBL_DESTMOD_PHYS (0x00000000) +#define IOAPIC_REDTBL_INTPOL_HIGH (0x00000000) +#define IOAPIC_REDTBL_INTPOL_LOW (0x00002000) +#define IOAPIC_REDTBL_IRR (0x00004000) +#define IOAPIC_REDTBL_TRIGGER_EDGE (0x00000000) +#define IOAPIC_REDTBL_TRIGGER_LEVEL (0x00008000) +#define IOAPIC_REDTBL_MASK (0x00010000) /* WDT (Watchdog Timer) Registers */ -#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0) -#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4) -#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8) -#define WDT_CONTROL_ENABLE_BIT BIT(17) +#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0) +#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4) +#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8) +#define WDT_CONTROL_ENABLE_BIT BIT(17) /* LAPIC registers */ -#define LAPIC_EOI_REG 0xFEE000B0 -#define LAPIC_ISR_REG 0xFEE00170 -#define LAPIC_IRR_REG (ISH_LAPIC_BASE + 0x200) -#define LAPIC_ESR_REG (ISH_LAPIC_BASE + 0x280) -#define LAPIC_ERR_RECV_ILLEGAL BIT(6) -#define LAPIC_ICR_REG (ISH_LAPIC_BASE + 0x300) +/* Bare address needed for assembler (ISH_LAPIC_BASE + 0xB0) */ +#define LAPIC_EOI_REG_ADDR 0xFEE000B0 +#define LAPIC_EOI_REG REG32(LAPIC_EOI_REG_ADDR) +#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x170) +#define LAPIC_IRR_REG REG32(ISH_LAPIC_BASE + 0x200) +#define LAPIC_ESR_REG REG32(ISH_LAPIC_BASE + 0x280) +#define LAPIC_ERR_RECV_ILLEGAL BIT(6) +#define LAPIC_ICR_REG REG32(ISH_LAPIC_BASE + 0x300) /* SRAM control registers */ #define ISH_SRAM_CTRL_BASE 0x00500000 |