diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2019-03-21 14:29:14 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-28 14:14:06 -0700 |
| commit | 60e9071a9ba8f773d33c076e0b4fb1956d285efd (patch) | |
| tree | 833a64f6fb60156095a88a153e7b6d45f12b01a1 /chip | |
| parent | 1b2426b5186d69cb53d327dfdc4795376686493a (diff) | |
| download | chrome-ec-60e9071a9ba8f773d33c076e0b4fb1956d285efd.tar.gz | |
stm32f0: Allow per-channel sampling rate setting
Currently, one sampling rate is set for all channels.
This patch allows a board to select a different sampling rate per
channel.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=Verify intended sampling rate is used for USBC_THERM on Flapjack.
Change-Id: I9f791f2865ef6f479ec02dbf1440cd744e280c7b
Reviewed-on: https://chromium-review.googlesource.com/1535116
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/adc-stm32f0.c | 8 | ||||
| -rw-r--r-- | chip/stm32/adc_chip.h | 3 |
2 files changed, 7 insertions, 4 deletions
diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c index 3836767d1f..c448b4b42f 100644 --- a/chip/stm32/adc-stm32f0.c +++ b/chip/stm32/adc-stm32f0.c @@ -22,7 +22,7 @@ struct adc_profile_t { /* Register values. */ uint32_t cfgr1_reg; uint32_t cfgr2_reg; - uint32_t smpr_reg; + uint32_t smpr_reg; /* Default Sampling Rate */ uint32_t ier_reg; /* DMA config. */ const struct dma_option *dma_option; @@ -69,7 +69,7 @@ static const struct adc_profile_t profile = { }; #endif -static void adc_init(void) +static void adc_init(const struct adc_t *adc) { /* * If clock is already enabled, and ADC module is enabled @@ -93,7 +93,7 @@ static void adc_init(void) /* clock is ADCCLK (ADEN must be off when writing this reg) */ STM32_ADC_CFGR2 = profile.cfgr2_reg; /* Sampling time */ - STM32_ADC_SMPR = profile.smpr_reg; + STM32_ADC_SMPR = adc->sample_rate ? adc->sample_rate : profile.smpr_reg; /* * ADC enable (note: takes 4 ADC clocks between end of calibration @@ -294,7 +294,7 @@ int adc_read_channel(enum adc_channel ch) mutex_lock(&adc_lock); - adc_init(); + adc_init(adc); if (adc_watchdog_enabled()) { restore_watchdog = 1; diff --git a/chip/stm32/adc_chip.h b/chip/stm32/adc_chip.h index 7b40535ac0..7d67ce2c6f 100644 --- a/chip/stm32/adc_chip.h +++ b/chip/stm32/adc_chip.h @@ -8,6 +8,8 @@ #ifndef __CROS_EC_ADC_CHIP_H #define __CROS_EC_ADC_CHIP_H +#include "stdint.h" + /* Data structure to define ADC channels. */ struct adc_t { const char *name; @@ -15,6 +17,7 @@ struct adc_t { int factor_div; int shift; int channel; + uint32_t sample_rate; /* Sampling Rate of the channel */ }; /* |