diff options
| author | tim <tim2.lin@ite.corp-partner.google.com> | 2019-06-27 17:48:03 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-07-02 18:28:38 +0000 |
| commit | d92daea73957789df43e458d31fadae7d2c64989 (patch) | |
| tree | 3b0d0560851da868e3354169ea809e5ea5be8f4f /chip | |
| parent | 587eb9d49b7642df83916f515f2d7adbafd3d1d1 (diff) | |
| download | chrome-ec-d92daea73957789df43e458d31fadae7d2c64989.tar.gz | |
it83xx/i2c_slave: the DMA registers have updated on IT8xxx2
The DMA read and write target address registers have changed.
BUG=none
BRANCH=none
TEST=Testing on IT8320dx and IT83202 EVB.
Change-Id: I9e63c3f7f402ed22c461eb86daa5eba0e6dcb58e
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660071
Commit-Queue: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/it83xx/i2c_slave.c | 34 | ||||
| -rw-r--r-- | chip/it83xx/registers.h | 4 |
2 files changed, 33 insertions, 5 deletions
diff --git a/chip/it83xx/i2c_slave.c b/chip/it83xx/i2c_slave.c index bce86d25b8..1902285959 100644 --- a/chip/it83xx/i2c_slave.c +++ b/chip/it83xx/i2c_slave.c @@ -230,6 +230,7 @@ void i2c_slave_enable(int port, uint8_t slv_addr) /* Enhanced I2C slave channel D, E, F DMA mode */ else { int ch, idx; + uint32_t in_data_addr, out_data_addr; /* Get enhanced i2c channel */ ch = i2c_slv_ctrl[port].offset / I2C_ENHANCED_CH_INTERVAL; @@ -280,13 +281,36 @@ void i2c_slave_enable(int port, uint8_t slv_addr) memset(in_data[idx], 0, I2C_MAX_BUFFER_SIZE); memset(out_data[idx], 0, I2C_MAX_BUFFER_SIZE); + if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) { + in_data_addr = (uint32_t)in_data[idx] & 0xffffff; + out_data_addr = (uint32_t)out_data[idx] & 0xffffff; + } else { + in_data_addr = (uint32_t)in_data[idx] & 0xfff; + out_data_addr = (uint32_t)out_data[idx] & 0xfff; + } + /* DMA write target address register */ - IT83XX_I2C_RAMHA(ch) = ((uint32_t)in_data[idx] >> 8) & 0x0F; - IT83XX_I2C_RAMLA(ch) = (uint32_t)in_data[idx] & 0xFF; + IT83XX_I2C_RAMHA(ch) = in_data_addr >> 8; + IT83XX_I2C_RAMLA(ch) = in_data_addr; - /* DMA read target address register */ - IT83XX_I2C_RAMHA2(ch) = ((uint32_t)out_data[idx] >> 8) & 0x0F; - IT83XX_I2C_RAMLA2(ch) = (uint32_t)out_data[idx] & 0xFF; + if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) { + /* + * DMA write target address register + * for high order byte + */ + IT83XX_I2C_RAMH2A(ch) = in_data_addr >> 16; + /* + * DMA read target address register + * for high order byte + */ + IT83XX_I2C_CMD_ADDH2(ch) = out_data_addr >> 16; + IT83XX_I2C_CMD_ADDH(ch) = out_data_addr >> 8; + IT83XX_I2C_CMD_ADDL(ch) = out_data_addr; + } else { + /* DMA read target address register */ + IT83XX_I2C_RAMHA2(ch) = out_data_addr >> 8; + IT83XX_I2C_RAMLA2(ch) = out_data_addr; + } /* I2C module enable and command queue mode */ IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN | diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 9a2015263e..077bd794cf 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1219,6 +1219,10 @@ enum bram_indices { #define IT83XX_I2C_RAMLA(ch) REG8(IT83XX_I2C_BASE+0x24+(ch << 7)) #define IT83XX_I2C_RAMHA2(ch) REG8(IT83XX_I2C_BASE+0x2B+(ch << 7)) #define IT83XX_I2C_RAMLA2(ch) REG8(IT83XX_I2C_BASE+0x2C+(ch << 7)) +#define IT83XX_I2C_CMD_ADDH(ch) REG8(IT83XX_I2C_BASE+0x25+(ch << 7)) +#define IT83XX_I2C_CMD_ADDL(ch) REG8(IT83XX_I2C_BASE+0x26+(ch << 7)) +#define IT83XX_I2C_RAMH2A(ch) REG8(IT83XX_I2C_BASE+0x50+(ch << 7)) +#define IT83XX_I2C_CMD_ADDH2(ch) REG8(IT83XX_I2C_BASE+0x52+(ch << 7)) enum i2c_channels { IT83XX_I2C_CH_A, /* GPIO.B3/B4 */ |