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| author | Scott Collyer <scollyer@google.com> | 2020-05-02 16:02:28 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-07-31 01:00:02 +0000 |
| commit | 8fcb7da8faeb8ca6f104af0164858e3e75d026c0 (patch) | |
| tree | 96de4f1e4c88ec901f5e298091f5f8d6d515cb0f /chip | |
| parent | 843ccb38cbf8488fac1797dd474b03c40dd359f1 (diff) | |
| download | chrome-ec-8fcb7da8faeb8ca6f104af0164858e3e75d026c0.tar.gz | |
stm32g4: Set uart frequency and enable clocks for stm32g4
This CL adds changes to enable clocks and configure the uart speed for
stm32g4 chip family.
BUG=b:148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I5600ed64867192fe77fd85fc3dbc0a63f912d738
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195550
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/uart.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index f20805f7e5..39727d71f1 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -247,7 +247,7 @@ static void uart_freq_change(void) #if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \ defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_FAMILY_STM32F4) + defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32G4) if (div / 16 > 0) { /* * CPU clock is high enough to support x16 oversampling. @@ -286,10 +286,10 @@ void uart_init(void) #else STM32_RCC_D2CCIP2R |= STM32_RCC_D2CCIP2_USART234578SEL_HSI; #endif /* UARTN */ -#elif defined(CHIP_FAMILY_STM32L4) +#elif defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32G4) /* USART1 clock source from SYSCLK */ STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_USART1SEL_MASK; - STM32_RCC_CCIPR |= + STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_UART_SYSCLK << STM32_RCC_CCIPR_USART1SEL_SHIFT); /* LPUART1 clock source from SYSCLK */ STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_LPUART1SEL_MASK; |