diff options
| author | Bhanu Prakash Maiya <bhanumaiya@google.com> | 2020-09-23 22:46:09 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-25 04:59:25 +0000 |
| commit | 9cf30804f85c8029c25944b6c8db4d6e242e21f8 (patch) | |
| tree | 7037c8087ad2271d77be65532a0443e28e08befc /chip | |
| parent | 9273bed1858368e4c550868987cf8968f9f85313 (diff) | |
| download | chrome-ec-9cf30804f85c8029c25944b6c8db4d6e242e21f8.tar.gz | |
Bloonchipper: Reduce usart transport's response size to 0x100
Bloonchipper firmware uses usart_host_command.c to communicate with Zork's
AP. On AMD SoC we found there is a 256 byte UART FIFO limitation with
Designware's UART IP. Typically DMA should have solved this issue but
looks like Picasso and Dali, UART DMA is not working at expected. This
is causing timeout issues with EC responses > 256 bytes. This patch will
limit the response size to 256 bytes which ensures that AP RX packets
always stay within FIFO limits. Currently UART based host command
transport is only used by FPMCU Dragonclaw STM32 design.
BRANCH=none
BUG=b:160208269
TEST=1. Run bloonchipper binary on Zork FPMCU devices.
2. Check PCO/DALI do not throw UART DMA overrun interrupt.
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
Change-Id: I0b99d25cf7d2dd163d05c35585064ad5e61a91ee
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428203
Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@googlers.com>
Tested-by: Bhanu Prakash Maiya <bhanumaiya@googlers.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@googlers.com>
Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@googlers.com>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/usart_host_command.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/chip/stm32/usart_host_command.c b/chip/stm32/usart_host_command.c index c5b6e2990f..f4d6a65fc4 100644 --- a/chip/stm32/usart_host_command.c +++ b/chip/stm32/usart_host_command.c @@ -51,11 +51,11 @@ /* * Max data size for a version 3 request/response packet. This is big enough - * to handle a request/response header, flash write offset/size, and 512 bytes - * of flash data. + * to handle a request/response header, flash write offset/size and 512 bytes + * of request payload or 224 bytes of response payload. */ #define USART_MAX_REQUEST_SIZE 0x220 -#define USART_MAX_RESPONSE_SIZE 0x220 +#define USART_MAX_RESPONSE_SIZE 0x100 /* * FIFO size for USART DMA. Should be big enough to handle worst case |