chip/mt8192_scp: make all cache operations inline

Makes all cache operations inline.

BRANCH=none
BUG=b:175512991
TEST=make BOARD=asurada_scp

Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I6d2e8752b4be63257854630a83c74aca21e0d799
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592298
Reviewed-by: Ting Shen <phoenixshen@chromium.org>

2 files changed, 97 insertions, 110 deletions

diff --git a/chip/mt8192_scp/cache.c b/chip/mt8192_scp/cache.c
index 7dcf0850f9..62147590fe 100644
--- a/chip/mt8192_scp/cache.c
+++ b/chip/mt8192_scp/cache.c
@@ -4,100 +4,8 @@
  */
 
 #include "cache.h"
-#include "common.h"
-#include "compile_time_macros.h"
 #include "console.h"
 #include "csr.h"
-#include "util.h"
-
-/* rs1 0~31 register X0~X31 */
-#define COP(rs1) (((rs1) << 15) | 0x400f)
-
-#define COP_OP_BARRIER_ICACHE		0x0
-#define COP_OP_INVALIDATE_ICACHE	0x8
-#define COP_OP_INVALIDATE_ICACHE_ADDR	0x9
-
-#define COP_OP_BARRIER_DCACHE		0x10
-#define COP_OP_WRITEBACK_DCACHE		0x14
-#define COP_OP_WRITEBACK_DCACHE_ADDR	0x15
-#define COP_OP_INVALIDATE_DCACHE	0x18
-#define COP_OP_INVALIDATE_DCACHE_ADDR	0x19
-/* FLUSH = WRITEBACK + INVALIDATE */
-#define COP_OP_FLUSH_DCACHE		0x1C
-#define COP_OP_FLUSH_DCACHE_ADDR	0x1D
-
-inline static void cache_op_all(uint32_t op)
-{
-	register int t0 asm("t0") = op;
-	asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
-}
-
-static int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op)
-{
-	size_t offset;
-	register int t0 asm("t0");
-
-	/* NOTE: cache operations must use 32 byte aligned address */
-	if (addr & GENMASK(3, 0))
-		return EC_ERROR_INVAL;
-
-	for (offset = 0; offset < length; offset += 4) {
-		t0 = addr + offset + op;
-		asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
-	}
-
-	return EC_SUCCESS;
-}
-
-void cache_barrier_icache(void)
-{
-	cache_op_all(COP_OP_BARRIER_ICACHE);
-}
-
-void cache_invalidate_icache(void)
-{
-	cache_op_all(COP_OP_INVALIDATE_ICACHE);
-}
-
-int cache_invalidate_icache_range(uintptr_t addr, uint32_t length)
-{
-	return cache_op_addr(addr, length, COP_OP_INVALIDATE_ICACHE_ADDR);
-}
-
-void cache_barrier_dcache(void)
-{
-	cache_op_all(COP_OP_BARRIER_DCACHE);
-}
-
-void cache_writeback_dcache(void)
-{
-	cache_op_all(COP_OP_WRITEBACK_DCACHE);
-}
-
-int cache_writeback_dcache_range(uintptr_t addr, uint32_t length)
-{
-	return cache_op_addr(addr, length, COP_OP_WRITEBACK_DCACHE_ADDR);
-}
-
-void cache_invalidate_dcache(void)
-{
-	cache_op_all(COP_OP_INVALIDATE_DCACHE);
-}
-
-int cache_invalidate_dcache_range(uintptr_t addr, uint32_t length)
-{
-	return cache_op_addr(addr, length, COP_OP_INVALIDATE_DCACHE_ADDR);
-}
-
-void cache_flush_dcache(void)
-{
-	cache_op_all(COP_OP_FLUSH_DCACHE);
-}
-
-int cache_flush_dcache_range(uintptr_t addr, uint32_t length)
-{
-	return cache_op_addr(addr, length, COP_OP_FLUSH_DCACHE_ADDR);
-}
 
 extern struct mpu_entry mpu_entries[];
 
diff --git a/chip/mt8192_scp/cache.h b/chip/mt8192_scp/cache.h
index 633937aa35..f5a9d55489 100644
--- a/chip/mt8192_scp/cache.h
+++ b/chip/mt8192_scp/cache.h
@@ -6,39 +6,118 @@
 #ifndef __CROS_EC_CACHE_H
 #define __CROS_EC_CACHE_H
 
+#include "common.h"
 #include "csr.h"
 #include "stdint.h"
+#include "util.h"
 
-struct mpu_entry {
-	/* 1k alignment and the address is inclusive */
-	uintptr_t start_addr;
-	/* 1k alignment in 4GB boundary and non-inclusive */
-	uintptr_t end_addr;
-	/* MPU_ATTR */
-	uint32_t attribute;
-};
+/* rs1 0~31 register X0~X31 */
+#define COP(rs1) (((rs1) << 15) | 0x400f)
+
+#define COP_OP_BARRIER_ICACHE		0x0
+#define COP_OP_INVALIDATE_ICACHE	0x8
+#define COP_OP_INVALIDATE_ICACHE_ADDR	0x9
+
+#define COP_OP_BARRIER_DCACHE		0x10
+#define COP_OP_WRITEBACK_DCACHE		0x14
+#define COP_OP_WRITEBACK_DCACHE_ADDR	0x15
+#define COP_OP_INVALIDATE_DCACHE	0x18
+#define COP_OP_INVALIDATE_DCACHE_ADDR	0x19
+/* FLUSH = WRITEBACK + INVALIDATE */
+#define COP_OP_FLUSH_DCACHE		0x1C
+#define COP_OP_FLUSH_DCACHE_ADDR	0x1D
+
+static inline void cache_op_all(uint32_t op)
+{
+	register int t0 asm("t0") = op;
+	asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
+}
+
+static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op)
+{
+	size_t offset;
+	register int t0 asm("t0");
+
+	/* NOTE: cache operations must use 32 byte aligned address */
+	if (addr & GENMASK(3, 0))
+		return EC_ERROR_INVAL;
+
+	for (offset = 0; offset < length; offset += 4) {
+		t0 = addr + offset + op;
+		asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0));
+	}
+
+	return EC_SUCCESS;
+}
 
 /* memory barrier of I$ */
-void cache_barrier_icache(void);
+static inline void cache_barrier_icache(void)
+{
+	cache_op_all(COP_OP_BARRIER_ICACHE);
+}
+
 /* invalidate all I$ */
-void cache_invalidate_icache(void);
+static inline void cache_invalidate_icache(void)
+{
+	cache_op_all(COP_OP_INVALIDATE_ICACHE);
+}
+
 /* invalidate a range of I$ */
-int cache_invalidate_icache_range(uintptr_t addr, uint32_t length);
+static inline int cache_invalidate_icache_range(uintptr_t addr, uint32_t length)
+{
+	return cache_op_addr(addr, length, COP_OP_INVALIDATE_ICACHE_ADDR);
+}
 
 /* memory barrier of D$ */
-void cache_barrier_dcache(void);
+static inline void cache_barrier_dcache(void)
+{
+	cache_op_all(COP_OP_BARRIER_DCACHE);
+}
+
 /* writeback all D$ */
-void cache_writeback_dcache(void);
+static inline void cache_writeback_dcache(void)
+{
+	cache_op_all(COP_OP_WRITEBACK_DCACHE);
+}
+
 /* writeback a range of D$ */
-int cache_writeback_dcache_range(uintptr_t addr, uint32_t length);
+static inline int cache_writeback_dcache_range(uintptr_t addr, uint32_t length)
+{
+	return cache_op_addr(addr, length, COP_OP_WRITEBACK_DCACHE_ADDR);
+}
+
 /* invalidate all D$ */
-void cache_invalidate_dcache(void);
+static inline void cache_invalidate_dcache(void)
+{
+	cache_op_all(COP_OP_INVALIDATE_DCACHE);
+}
+
 /* invalidate a range of D$ */
-int cache_invalidate_dcache_range(uintptr_t addr, uint32_t length);
+static inline int cache_invalidate_dcache_range(uintptr_t addr, uint32_t length)
+{
+	return cache_op_addr(addr, length, COP_OP_INVALIDATE_DCACHE_ADDR);
+}
+
 /* writeback and invalidate all D$ */
-void cache_flush_dcache(void);
+static inline void cache_flush_dcache(void)
+{
+	cache_op_all(COP_OP_FLUSH_DCACHE);
+}
+
 /* writeback and invalidate a range of D$ */
-int cache_flush_dcache_range(uintptr_t addr, uint32_t length);
+static inline int cache_flush_dcache_range(uintptr_t addr, uint32_t length)
+{
+	return cache_op_addr(addr, length, COP_OP_FLUSH_DCACHE_ADDR);
+}
+
+struct mpu_entry {
+	/* 1k alignment and the address is inclusive */
+	uintptr_t start_addr;
+	/* 1k alignment in 4GB boundary and non-inclusive */
+	uintptr_t end_addr;
+	/* MPU_ATTR */
+	uint32_t attribute;
+};
 
 void cache_init(void);