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| author | Wealian Liao <whliao@nuvoton.corp-partner.google.com> | 2020-12-17 18:43:51 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-12-28 18:03:26 +0000 |
| commit | b490e372ec3d321b71d949cb48f274c0f784b622 (patch) | |
| tree | f79ca7d78f8d14316901ff2512d46981e8073852 /chip | |
| parent | 7cf197d455b3afc565f03abf0b911fd4a208a52e (diff) | |
| download | chrome-ec-b490e372ec3d321b71d949cb48f274c0f784b622.tar.gz | |
npcx9: remove unnecessary default CONFIGs for internal flash
In npcx9, the internal flash is accessed via FIU/UMA (implementing in
chip/npcx/flash.c). It won’t use the common/spi_flash.c to access the
internal flash. This CL remove the two default configs related to the
SPI flash in the npcx9 chip config and fix the npcx9_evb setting for
the SPI flash.
BRANCH=none
BUG=b:165777478
TEST=buildall pass
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I7c525791d001fa2833b7d895f277768948783938
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600807
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/npcx/config_chip-npcx9.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h index 9f7b0f52d0..a13723f980 100644 --- a/chip/npcx/config_chip-npcx9.h +++ b/chip/npcx/config_chip-npcx9.h @@ -98,8 +98,6 @@ #endif /* Internal spi-flash setting */ -#define CONFIG_SPI_FLASH_PORT 0 -#define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */ #define CONFIG_FLASH_SIZE 0x00080000 /* 512 KB internal spi flash */ |