stm32: convert to CONFIG_CHIP_MEMORY_REGIONS

Remove the former special case for USB RAM
Add additional RAM regions for STM32H7.

For USB RAM, add an explicit alignment directive to ensure we always meet
the 8-byte boundary hardware constraint for the BTABLE.
This was already true because we put the .usb_ram.btable section first.
I keep this property by alpha-sorting the sections but makes it more
explicit by adding a 2-digit numeric prefix: e.g. 00_firstsection,
99_lastsection.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, along with the following CLs, run the firmware with
large arrays in special AHB memory regions.
TEST=build all targets with and without the patch and verify that all
smap files are identical.

Change-Id: I9ee7f519a13cb14ba9997220f22180028f9c0175
Reviewed-on: https://chromium-review.googlesource.com/946369
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>

4 files changed, 22 insertions, 4 deletions

diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index 1d7f95115d..4a2f686e6b 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -79,6 +79,9 @@
 #include "config_std_internal_flash.h"
 #endif
 
+/* Additional special purpose regions (USB RAM and other special SRAMs) */
+#define CONFIG_CHIP_MEMORY_REGIONS
+
 /* System stack size */
 #if defined(CHIP_VARIANT_STM32F05X)
 #define CONFIG_STACK_SIZE 768
diff --git a/chip/stm32/memory_regions.inc b/chip/stm32/memory_regions.inc
new file mode 100644
index 0000000000..eaa9fc71f3
--- /dev/null
+++ b/chip/stm32/memory_regions.inc
@@ -0,0 +1,16 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef CONFIG_USB_RAM_SIZE
+REGION(usb_ram, rw, CONFIG_USB_RAM_BASE, \
+       CONFIG_USB_RAM_SIZE * CONFIG_USB_RAM_ACCESS_SIZE / 2)
+#endif /* CONFIG_USB_RAM_SIZE */
+#ifdef CHIP_VARIANT_STM32H7X3
+REGION(itcm,   wx, 0x00000000, 0x10000) /* CPU ITCM: 64kB */
+REGION(dtcm,   rw, 0x20000000, 0x20000) /* CPU DTCM: 128kB */
+REGION(ahb,    rw, 0x30000000, 0x48000) /* AHB-SRAM1-3: 288 kB */
+REGION(ahb4,   rw, 0x38000000, 0x10000) /* AHB-SRAM4: 64kB */
+REGION(backup, rw, 0x38000000, 0x01000) /* Backup RAM: 4kB */
+#endif /* CHIP_VARIANT_STM32H7X3 */
diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c
index 560ca3da2d..c8768823d7 100644
--- a/chip/stm32/usb.c
+++ b/chip/stm32/usb.c
@@ -90,8 +90,7 @@ const uint8_t usb_string_desc[] = {
 };
 
 /* Endpoint table in USB controller RAM */
-struct stm32_endpoint btable_ep[USB_EP_COUNT]
-	__attribute__((section(".usb_ram.btable")));
+struct stm32_endpoint btable_ep[USB_EP_COUNT] __aligned(8) __usb_btable;
 /* Control endpoint (EP0) buffers */
 static usb_uint ep0_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
 static usb_uint ep0_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram;
diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h
index 0ba7fb369d..fb7b5d546b 100644
--- a/chip/stm32/usb_hw.h
+++ b/chip/stm32/usb_hw.h
@@ -29,7 +29,7 @@ typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint;
 extern usb_uint __usb_ram_start[];
 
 /* Attribute to define a buffer variable in USB RAM */
-#define __usb_ram __attribute__((section(".usb_ram.data")))
+#define __usb_ram __attribute__((section(".usb_ram.99_data")))
 
 struct stm32_endpoint {
 	volatile usb_uint tx_addr;
@@ -41,7 +41,7 @@ struct stm32_endpoint {
 extern struct stm32_endpoint btable_ep[];
 
 /* Attribute to put the endpoint table in USB RAM */
-#define __usb_btable __attribute__((section(".usb_ram.btable")))
+#define __usb_btable __attribute__((section(".usb_ram.00_btable")))
 
 /* Read from USB RAM into a usb_setup_packet struct */
 struct usb_setup_packet;