baytrail: Workaround for stuck boot process

In some cases, the system will boot to S0 from the point of view of
the EC, but PLTRST# will never deassert.  Work around this by waiting
50 ms for PLTRST# to deassert.  If it doesn't, force the chipset all
the way down by deasserting RSMRST#, then pulse the power button to
turn it back on.

Also add a powerfail debug command to simulate this failure event, so
that the recovery process can be tested.

Add API to the LPC module to get the state of PLTRST#, and to the
power button state machine to force it released when we shut down the
chipset and and force another power button pulse as we reset the
chipset.

BUG=chrome-os-partner:28422
BRANCH=baytrail
TEST=1. Boot system.  Should boot normally.  Shut system down.
     2. powerfail
     3. Boot system.  On the EC console, should see the system come up,
        go back down through G3S5, then come back up.  From the user's
	point of view, it just boots.
     1. Boot system.  Should boot normally.  (That is, powerfail is not sticky)

Change-Id: Ia57f196606f79b9f2fce7d9cd109ab932c3571aa
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/197523
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 6 insertions, 1 deletions

diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index 3f1d878457..ef273be8b8 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -427,6 +427,11 @@ uint32_t lpc_get_host_event_mask(enum lpc_host_event_type type)
 	return event_mask[type];
 }
 
+int lpc_get_pltrst_asserted(void)
+{
+	return (LM4_LPC_LPCSTS & (1<<10)) ? 1 : 0;
+}
+
 /**
  * Handle write to ACPI I/O port
  *
@@ -618,7 +623,7 @@ void lpc_interrupt(void)
 		}
 
 		CPRINTF("[%T LPC RESET# %sasserted]\n",
-			(LM4_LPC_LPCSTS & (1<<10)) ? "" : "de");
+			lpc_get_pltrst_asserted() ? "" : "de");
 	}
 }
 DECLARE_IRQ(LM4_IRQ_LPC, lpc_interrupt, 2);