diff options
| author | Tinghan Shen <tinghan.shen@mediatek.com> | 2021-03-05 20:56:14 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-08 07:48:36 +0000 |
| commit | f7637b3f78d82061922f2e5d28ca9d812e2fd51e (patch) | |
| tree | c5ed6a5f9d982c76838ca955f01b46103505954e /chip | |
| parent | 4d2c6d035a921dd0293384b3733682e2c0de45a9 (diff) | |
| download | chrome-ec-f7637b3f78d82061922f2e5d28ca9d812e2fd51e.tar.gz | |
chip/mt8192_scp: use ULPOSC1 div 8 instead of 26M for timer
26M clock cannot be used when AP enters S3. Uses ULPOSC1 / 8 instead.
Timer uses BCLK which selects ULPOSC1 / 8 as clock source which is
260M / 8 = 32.5M.
BRANCH=none
BUG=b:181629273
TEST=powerd_dbus_suspend
Change-Id: I98bcabe47317dc9739bfb61d12defd99d9a14ede
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2739006
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/mt8192_scp/clock.c | 3 | ||||
| -rw-r--r-- | chip/mt8192_scp/hrtimer.c | 6 | ||||
| -rw-r--r-- | chip/mt8192_scp/registers.h | 5 |
3 files changed, 11 insertions, 3 deletions
diff --git a/chip/mt8192_scp/clock.c b/chip/mt8192_scp/clock.c index ee7970a71a..55813224de 100644 --- a/chip/mt8192_scp/clock.c +++ b/chip/mt8192_scp/clock.c @@ -321,6 +321,9 @@ void clock_init(void) /* select ULPOSC2 high speed CPU clock */ clock_select_clock(SCP_CLK_ULPOSC2); + /* select BCLK to use ULPOSC1 / 8 = 260MHz / 8 = 32.5MHz */ + SCP_BCLK_CK_SEL = BCLK_CK_SEL_ULPOSC_DIV8; + /* enable default clock gate */ SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 | CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK; diff --git a/chip/mt8192_scp/hrtimer.c b/chip/mt8192_scp/hrtimer.c index a3f0ed3298..89ffaa2fca 100644 --- a/chip/mt8192_scp/hrtimer.c +++ b/chip/mt8192_scp/hrtimer.c @@ -19,7 +19,7 @@ #define TIMER_SYSTEM 5 #define TIMER_EVENT 3 -#define TIMER_CLOCK_MHZ 26 +#define TIMER_CLOCK_MHZ 32.5 #define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1) /* High 32-bit for system timer. */ @@ -129,14 +129,14 @@ int __hw_clock_source_init(uint32_t start_t) timer_reset(t); /* System timestamp timer */ - timer_set_clock(TIMER_SYSTEM, TIMER_CLK_SRC_26M); + timer_set_clock(TIMER_SYSTEM, TIMER_CLK_SRC_BCLK); sys_high = TIMER_CLOCK_MHZ - 1; timer_set_reset_value(TIMER_SYSTEM, 0xffffffff); task_enable_irq(SCP_IRQ_TIMER(TIMER_SYSTEM)); timer_enable(TIMER_SYSTEM); /* Event tick timer */ - timer_set_clock(TIMER_EVENT, TIMER_CLK_SRC_26M); + timer_set_clock(TIMER_EVENT, TIMER_CLK_SRC_BCLK); task_enable_irq(SCP_IRQ_TIMER(TIMER_EVENT)); return SCP_IRQ_TIMER(TIMER_SYSTEM); diff --git a/chip/mt8192_scp/registers.h b/chip/mt8192_scp/registers.h index cde931a2ba..a64c446c8c 100644 --- a/chip/mt8192_scp/registers.h +++ b/chip/mt8192_scp/registers.h @@ -92,6 +92,11 @@ #define UART_CK_SW_STATUS_26M BIT(0) #define UART_CK_SW_STATUS_32K BIT(1) #define UART_CK_SW_STATUS_ULPOS BIT(2) +/* BCLK clock select */ +#define SCP_BCLK_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0048) +#define BCLK_CK_SEL_SYS_DIV8 0 +#define BCLK_CK_SEL_32K 1 +#define BCLK_CK_SEL_ULPOSC_DIV8 2 /* VREQ control */ #define SCP_CPU_VREQ_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0054) #define VREQ_SEL BIT(0) |