diff options
| author | Keith Short <keithshort@chromium.org> | 2021-08-06 14:26:58 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-19 23:28:51 +0000 |
| commit | ed39a99992faae7f576aa2a73feb01a0769c36a2 (patch) | |
| tree | a1b7cd6f47a03b64b62eac140e2e4c9ac16403be /chip | |
| parent | f2809b72c935beb26e1b29f6fa01fb851cadc492 (diff) | |
| download | chrome-ec-ed39a99992faae7f576aa2a73feb01a0769c36a2.tar.gz | |
config: rename CONFIG_HOSTCMD_SHI to CONFIG_HOST_INTERFACE_SHI
Rename CONFIG_HOSTCMD_SHI to CONFIG_HOST_INTERFACE_SHI. This makes the
host interface selection configs distinct from configs used to
enable/disable specific host commands.
BUG=b:195416058
BRANCH=main
TEST=compare_build.sh
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I35959149554f58c8911459dcd025720b6d66eb32
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095843
Tested-by: Michał Barnaś <mb@semihalf.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/npcx/build.mk | 2 | ||||
| -rw-r--r-- | chip/npcx/gpio-npcx5.c | 2 | ||||
| -rw-r--r-- | chip/npcx/gpio-npcx9.c | 2 | ||||
| -rw-r--r-- | chip/npcx/gpio.c | 2 | ||||
| -rw-r--r-- | chip/npcx/shi_chip.h | 8 |
5 files changed, 7 insertions, 9 deletions
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index f872b2d051..246ab84f34 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -35,7 +35,7 @@ chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o chip-$(CONFIG_HOSTCMD_X86)+=lpc.o chip-$(CONFIG_HOST_INTERFACE_ESPI)+=espi.o chip-$(CONFIG_PECI)+=peci.o -chip-$(CONFIG_HOSTCMD_SHI)+=shi.o +chip-$(CONFIG_HOST_INTERFACE_SHI)+=shi.o chip-$(CONFIG_CEC)+=cec.o # pwm functions are implemented with the fan functions chip-$(CONFIG_PWM)+=pwm.o diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c index 8e7c76abf1..9412aa9d9f 100644 --- a/chip/npcx/gpio-npcx5.c +++ b/chip/npcx/gpio-npcx5.c @@ -179,7 +179,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); -#ifdef CONFIG_HOSTCMD_SHI +#ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c index c5b7e900f7..31ed4e62ac 100644 --- a/chip/npcx/gpio-npcx9.c +++ b/chip/npcx/gpio-npcx9.c @@ -195,7 +195,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); -#ifdef CONFIG_HOSTCMD_SHI +#ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index e740f0aa9f..5f1e3c78b6 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -560,7 +560,7 @@ void gpio_pre_init(void) #endif /* Pin_Mux for LPC & SHI */ -#ifdef CONFIG_HOSTCMD_SHI +#ifdef CONFIG_HOST_INTERFACE_SHI /* Switching to eSPI mode for SHI interface */ NPCX_DEVCNT |= 0x08; /* Alternate Intel bus interface LPC/eSPI to GPIOs first */ diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h index c14aec196e..3fd73e8119 100644 --- a/chip/npcx/shi_chip.h +++ b/chip/npcx/shi_chip.h @@ -5,10 +5,9 @@ /* NPCX-specific SHI module for Chrome EC */ -#ifndef SHI_CHIP_H_ -#define SHI_CHIP_H_ +#ifndef __CROS_EC_SHI_CHIP_H_ +#define __CROS_EC_SHI_CHIP_H_ -#ifdef CONFIG_HOSTCMD_SHI /** * Called when the NSS level changes, signalling the start of a SHI * transaction. @@ -19,6 +18,5 @@ void shi_cs_event(enum gpio_signal signal); #ifdef NPCX_SHI_V2 void shi_cs_gpio_int(enum gpio_signal signal); #endif -#endif -#endif /* SHI_CHIP_H_ */ +#endif /* __CROS_EC_SHI_CHIP_H_ */ |