diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 15:57:52 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:42:55 -0700 |
| commit | bb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch) | |
| tree | f6ada087f62246c3a9547e649ac8846b0ed6d5ab /chip | |
| parent | 0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff) | |
| download | chrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz | |
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip')
100 files changed, 1123 insertions, 1123 deletions
diff --git a/chip/g/dcrypto/gcm.c b/chip/g/dcrypto/gcm.c index 18016de612..2caddf4741 100644 --- a/chip/g/dcrypto/gcm.c +++ b/chip/g/dcrypto/gcm.c @@ -46,7 +46,7 @@ static void gcm_init_iv( if (iv_len == 12) { memcpy(counter, iv, 12); - counter[3] = 1 << 24; + counter[3] = BIT(24); } else { size_t i; uint32_t len = iv_len; diff --git a/chip/g/gpio.c b/chip/g/gpio.c index 432608beea..79b40124d5 100644 --- a/chip/g/gpio.c +++ b/chip/g/gpio.c @@ -426,10 +426,10 @@ static void show_pinmux(const char *name, int i, int ofs) ccprintf("%08x: %s%-2d %2d %s%s%s%s ", GC_PINMUX_BASE_ADDR + i * 8 + ofs, name, i, sel, - (ctl & (1<<2)) ? " IN" : "", - (ctl & (1<<3)) ? " PD" : "", - (ctl & (1<<4)) ? " PU" : "", - (ctl & (1<<5)) ? " INV" : ""); + (ctl & BIT(2)) ? " IN" : "", + (ctl & BIT(3)) ? " PD" : "", + (ctl & BIT(4)) ? " PU" : "", + (ctl & BIT(5)) ? " INV" : ""); print_periph(sel); diff --git a/chip/g/i2cs.c b/chip/g/i2cs.c index 55aca1e85a..745853cdc2 100644 --- a/chip/g/i2cs.c +++ b/chip/g/i2cs.c @@ -73,7 +73,7 @@ #include "task.h" #include "tpm_log.h" -#define REGISTER_FILE_SIZE (1 << 6) /* 64 bytes. */ +#define REGISTER_FILE_SIZE BIT(6) /* 64 bytes. */ #define REGISTER_FILE_MASK (REGISTER_FILE_SIZE - 1) /* Console output macros */ diff --git a/chip/g/idle.c b/chip/g/idle.c index e46351d2f5..1ed16de4a4 100644 --- a/chip/g/idle.c +++ b/chip/g/idle.c @@ -202,7 +202,7 @@ static void idle_init(void) * If bus obfuscation is enabled disable sleep. */ if ((GR_FUSE(OBFUSCATION_EN) == 5) || - (GR_FUSE(FW_DEFINED_BROM_APPLYSEC) & (1 << 3)) || + (GR_FUSE(FW_DEFINED_BROM_APPLYSEC) & BIT(3)) || (runlevel_is_high() && GREAD(GLOBALSEC, OBFS_SW_EN))) { CPRINTS("bus obfuscation enabled disabling sleep"); idle_default = IDLE_WFI; diff --git a/chip/g/ite_flash.c b/chip/g/ite_flash.c index b805e09e6a..b4e1699a08 100644 --- a/chip/g/ite_flash.c +++ b/chip/g/ite_flash.c @@ -47,8 +47,8 @@ void generate_ite_sync(void) * 1 to be able to generate two necessary waveforms. */ both_zero = 0; - one_zero = 1 << 13; - zero_one = 1 << 12; + one_zero = BIT(13); + zero_one = BIT(12); both_one = one_zero | zero_one; /* Address of the mask byte register to use to set both pins. */ diff --git a/chip/g/pmu.c b/chip/g/pmu.c index 47b8341d5a..a324e6cee7 100644 --- a/chip/g/pmu.c +++ b/chip/g/pmu.c @@ -10,7 +10,7 @@ * RC Trim constants */ #define RCTRIM_RESOLUTION (12) -#define RCTRIM_LOAD_VAL (1 << 11) +#define RCTRIM_LOAD_VAL BIT(11) #define RCTRIM_RANGE_MAX (7 * 7) #define RCTRIM_RANGE_MIN (-8 * 7) #define RCTRIM_RANGE (RCTRIM_RANGE_MAX - RCTRIM_RANGE_MIN + 1) diff --git a/chip/g/registers.h b/chip/g/registers.h index 9c16df7f62..9127802db3 100644 --- a/chip/g/registers.h +++ b/chip/g/registers.h @@ -387,7 +387,7 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, */ #define GP_OUT(v) (GC_USB_GGPIO_GPO_MASK & ((v) << GC_USB_GGPIO_GPO_LSB)) #define GP_IN(v) (GC_USB_GGPIO_GPI_MASK & ((v) << GC_USB_GGPIO_GPI_LSB)) -#define GGPIO_WRITE(reg, val) GP_OUT(((1 << 15) | /* write bit */ \ +#define GGPIO_WRITE(reg, val) GP_OUT((BIT(15) | /* write bit */ \ (((val) & 0xFF) << 4) | /* value */ \ ((reg) & 0x0F))) /* register */ #define GGPIO_READ(reg) GP_OUT((reg) & 0x0F) /* register */ @@ -399,14 +399,14 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define USB_SEL_PHY0 0x00 /* bit 0 */ #define USB_SEL_PHY1 0x01 /* bit 0 */ #define USB_IDLE_PHY_CTRL_REG 1 /* register number */ -#define USB_FS_SUSPENDB (1 << 7) -#define USB_FS_EDGE_SEL (1 << 6) -#define USB_DM_PULLUP_EN (1 << 5) -#define USB_DP_RPU2_ENB (1 << 4) -#define USB_DP_RPU1_ENB (1 << 3) -#define USB_TX_OEB (1 << 2) -#define USB_TX_DPO (1 << 1) -#define USB_TX_DMO (1 << 0) +#define USB_FS_SUSPENDB BIT(7) +#define USB_FS_EDGE_SEL BIT(6) +#define USB_DM_PULLUP_EN BIT(5) +#define USB_DP_RPU2_ENB BIT(4) +#define USB_DP_RPU1_ENB BIT(3) +#define USB_TX_OEB BIT(2) +#define USB_TX_DPO BIT(1) +#define USB_TX_DMO BIT(0) #define GAHBCFG_DMA_EN (1 << GC_USB_GAHBCFG_DMAEN_LSB) #define GAHBCFG_GLB_INTR_EN (1 << GC_USB_GAHBCFG_GLBLINTRMSK_LSB) @@ -515,8 +515,8 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define DXEPCTL_USBACTEP (1 << GC_USB_DIEPCTL0_USBACTEP_LSB) #define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) #define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) -#define DXEPCTL_SET_D0PID (1 << 28) -#define DXEPCTL_SET_D1PID (1 << 29) +#define DXEPCTL_SET_D0PID BIT(28) +#define DXEPCTL_SET_D1PID BIT(29) #define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB) #define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB) @@ -528,12 +528,12 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define DOEPDMA_BS_HOST_BSY (3 << 30) #define DOEPDMA_BS_MASK (3 << 30) #define DOEPDMA_RXSTS_MASK (3 << 28) -#define DOEPDMA_LAST (1 << 27) -#define DOEPDMA_SP (1 << 26) -#define DOEPDMA_IOC (1 << 25) -#define DOEPDMA_SR (1 << 24) -#define DOEPDMA_MTRF (1 << 23) -#define DOEPDMA_NAK (1 << 16) +#define DOEPDMA_LAST BIT(27) +#define DOEPDMA_SP BIT(26) +#define DOEPDMA_IOC BIT(25) +#define DOEPDMA_SR BIT(24) +#define DOEPDMA_MTRF BIT(23) +#define DOEPDMA_NAK BIT(16) #define DOEPDMA_RXBYTES(n) (((n) & 0xFFFF) << 0) #define DOEPDMA_RXBYTES_MASK (0xFFFF << 0) @@ -543,9 +543,9 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define DIEPDMA_BS_HOST_BSY (3 << 30) #define DIEPDMA_BS_MASK (3 << 30) #define DIEPDMA_TXSTS_MASK (3 << 28) -#define DIEPDMA_LAST (1 << 27) -#define DIEPDMA_SP (1 << 26) -#define DIEPDMA_IOC (1 << 25) +#define DIEPDMA_LAST BIT(27) +#define DIEPDMA_SP BIT(26) +#define DIEPDMA_IOC BIT(25) #define DIEPDMA_TXBYTES(n) (((n) & 0xFFFF) << 0) #define DIEPDMA_TXBYTES_MASK (0xFFFF << 0) diff --git a/chip/g/signed_header.h b/chip/g/signed_header.h index 3ee4085a14..6096350a54 100644 --- a/chip/g/signed_header.h +++ b/chip/g/signed_header.h @@ -100,7 +100,7 @@ BUILD_ASSERT(offsetof(struct SignedHeader, info_chk_) == 1020); * * This convention is enforced at the key generation time. */ -#define G_SIGNED_FOR_PROD(h) ((h)->keyid & (1 << 2)) +#define G_SIGNED_FOR_PROD(h) ((h)->keyid & BIT(2)) #endif /* __CROS_EC_SIGNED_HEADER_H */ diff --git a/chip/g/sps.h b/chip/g/sps.h index b9684c4b90..5e95042a7e 100644 --- a/chip/g/sps.h +++ b/chip/g/sps.h @@ -19,7 +19,7 @@ enum sps_mode { }; /* Receive and transmit FIFO size and mask. */ -#define SPS_FIFO_SIZE (1 << 10) +#define SPS_FIFO_SIZE BIT(10) #define SPS_FIFO_MASK (SPS_FIFO_SIZE - 1) /* diff --git a/chip/g/usb_spi.h b/chip/g/usb_spi.h index 72364ab469..cedfe78485 100644 --- a/chip/g/usb_spi.h +++ b/chip/g/usb_spi.h @@ -77,9 +77,9 @@ enum usb_spi_request { /* USB SPI device bitmasks */ enum usb_spi { USB_SPI_DISABLE = 0, - USB_SPI_AP = (1 << 0), - USB_SPI_EC = (1 << 1), - USB_SPI_H1 = (1 << 2), + USB_SPI_AP = BIT(0), + USB_SPI_EC = BIT(1), + USB_SPI_H1 = BIT(2), USB_SPI_ALL = USB_SPI_AP | USB_SPI_EC | USB_SPI_H1 }; diff --git a/chip/host/host_test.h b/chip/host/host_test.h index 6eac0bc62e..1161b36ee7 100644 --- a/chip/host/host_test.h +++ b/chip/host/host_test.h @@ -9,7 +9,7 @@ #define __CROS_EC_HOST_TEST_H /* Emulator exit codes */ -#define EXIT_CODE_HIBERNATE (1 << 7) +#define EXIT_CODE_HIBERNATE BIT(7) /* Get emulator executable name */ const char *__get_prog_name(void); diff --git a/chip/ish/host_command_heci.c b/chip/ish/host_command_heci.c index 11435841c4..45e5f39fbd 100644 --- a/chip/ish/host_command_heci.c +++ b/chip/ish/host_command_heci.c @@ -114,7 +114,7 @@ static int heci_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = HECI_CROS_EC_LIMIT_PACKET_SIZE; r->max_response_packet_size = HECI_CROS_EC_RESPONSE_MAX; diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h index 463d3b38a6..ee26162518 100644 --- a/chip/ish/hpet.h +++ b/chip/ish/hpet.h @@ -48,9 +48,9 @@ * Use this register to see HPET timer are settled after a write. */ #define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + 0x160) -#define HPET_T1_CMP_SETTLING (1 << 8) -#define HPET_T1_CAP_SETTLING (1 << 5) -#define HPET_MAIN_COUNTER_SETTLING (1 << 2) +#define HPET_T1_CMP_SETTLING BIT(8) +#define HPET_T1_CAP_SETTLING BIT(5) +#define HPET_MAIN_COUNTER_SETTLING BIT(2) #define HPET_T1_SETTLING (HPET_T1_CAP_SETTLING | \ HPET_T1_CMP_SETTLING) diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c index 9574f38799..b7c471e802 100644 --- a/chip/ish/ipc_heci.c +++ b/chip/ish/ipc_heci.c @@ -58,25 +58,25 @@ #define MNG_ILLEGAL_CMD 0xFF /* Peripheral Interrupt Satus Register */ -#define IPC_PISR_HOST2ISH_BIT (1<<0) -#define IPC_PISR_PMC2ISH_BIT (1<<1) -#define IPC_PISR_CSME2ISH_BIT (1<<2) +#define IPC_PISR_HOST2ISH_BIT BIT(0) +#define IPC_PISR_PMC2ISH_BIT BIT(1) +#define IPC_PISR_CSME2ISH_BIT BIT(2) /* Peripheral Interrupt Mask Register */ -#define IPC_PIMR_HOST2ISH_BIT (1<<0) -#define IPC_PIMR_PMC2ISH_BIT (1<<1) -#define IPC_PIMR_CSME2ISH_BIT (1<<2) +#define IPC_PIMR_HOST2ISH_BIT BIT(0) +#define IPC_PIMR_PMC2ISH_BIT BIT(1) +#define IPC_PIMR_CSME2ISH_BIT BIT(2) -#define IPC_PIMR_ISH2HOST_CLR_BIT (1<<11) -#define IPC_PIMR_ISH2PMC_CLR_BIT (1<<12) -#define IPC_PIMR_ISH2CSME_CLR_BIT (1<<13) +#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11) +#define IPC_PIMR_ISH2PMC_CLR_BIT BIT(12) +#define IPC_PIMR_ISH2CSME_CLR_BIT BIT(13) /* Peripheral Interrupt DB(DoorBell) Clear Status Register */ -#define IPC_DB_CLR_STS_ISH2HOST_BIT (1<<0) -#define IPC_DB_CLR_STS_ISH2ISP_BIT (1<<2) -#define IPC_DB_CLR_STS_ISH2AUDIO_BIT (1<<3) -#define IPC_DB_CLR_STS_ISH2PMC_BIT (1<<8) -#define IPC_DB_CLR_STS_ISH2CSME_BIT (1<<16) +#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0) +#define IPC_DB_CLR_STS_ISH2ISP_BIT BIT(2) +#define IPC_DB_CLR_STS_ISH2AUDIO_BIT BIT(3) +#define IPC_DB_CLR_STS_ISH2PMC_BIT BIT(8) +#define IPC_DB_CLR_STS_ISH2CSME_BIT BIT(16) /* Doorbell */ #define IPC_DB_MSG_LENGTH_FIELD 0x3FF diff --git a/chip/ish/ish_i2c.h b/chip/ish/ish_i2c.h index d981b545ae..2b88524fda 100644 --- a/chip/ish/ish_i2c.h +++ b/chip/ish/ish_i2c.h @@ -154,11 +154,11 @@ enum { TX_BUFFER_DEPTH_OFFSET = 16, RX_BUFFER_DEPTH_OFFSET = 8, /* IC_INTR_MASK VALUES */ - M_RX_FULL = (1 << 2), - M_TX_EMPTY = (1 << 4), - M_TX_ABRT = (1 << 6), - M_STOP_DET = (1 << 9), - M_START_DET = (1 << 10), + M_RX_FULL = BIT(2), + M_TX_EMPTY = BIT(4), + M_TX_ABRT = BIT(6), + M_STOP_DET = BIT(9), + M_START_DET = BIT(10), IC_INTR_WRITE_MASK_VAL = (M_STOP_DET | M_TX_ABRT), IC_INTR_READ_MASK_VAL = (M_RX_FULL | M_TX_ABRT), DISABLE_INT = 0, diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 63c16fcdb8..9106463356 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -122,15 +122,15 @@ enum ish_i2c_port { /* PMU Registers */ #define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c) -#define VNN_REQ_IPC_HOST_WRITE (1 << 3) /* Power for IPC host write */ +#define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */ #define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40) -#define PMU_VNN_REQ_ACK_STATUS (1 << 0) /* VNN req and ack status */ +#define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */ #define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c) -#define PMU_RST_PREP_GET (1 << 0) -#define PMU_RST_PREP_AVAIL (1 << 1) -#define PMU_RST_PREP_INT_MASK (1 << 31) +#define PMU_RST_PREP_GET BIT(0) +#define PMU_RST_PREP_AVAIL BIT(1) +#define PMU_RST_PREP_INT_MASK BIT(31) /* CCU Registers */ #define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0) @@ -163,7 +163,7 @@ enum ish_i2c_port { #define LAPIC_ISR_REG 0xFEE00170 #define LAPIC_IRR_REG (ISH_LAPIC_BASE + 0x200) #define LAPIC_ESR_REG (ISH_LAPIC_BASE + 0x280) -#define LAPIC_ERR_RECV_ILLEGAL (1 << 6) +#define LAPIC_ERR_RECV_ILLEGAL BIT(6) #define LAPIC_ICR_REG (ISH_LAPIC_BASE + 0x300) #endif /* __CROS_EC_REGISTERS_H */ diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h index 11ea17cb82..86c6748f06 100644 --- a/chip/ish/uart_defs.h +++ b/chip/ish/uart_defs.h @@ -150,20 +150,20 @@ /* UART config flag, send to sc_io_control if the current UART line has HW * flow control lines connected. */ -#define UART_CONFIG_HW_FLOW_CONTROL (1<<0) +#define UART_CONFIG_HW_FLOW_CONTROL BIT(0) /* UART config flag for sc_io_control. If defined a sc_io_event_rx_msg is * raised only when the rx buffer is completely full. Otherwise, the event * is raised after a timeout is received on the UART line, * and all data received until now is provided. */ -#define UART_CONFIG_DELIVER_FULL_RX_BUF (1<<1) +#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1) /* UART config flag for sc_io_control. If defined a sc_io_event_rx_buf_depleted * is raised when all rx buffers that were added are full. Otherwise, no * event is raised. */ -#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF (1<<2) +#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2) #define UART_INT_DEVICES 2 #define UART_EXT_DEVICES 8 diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c index 6b8361dbdb..71f92c44e9 100644 --- a/chip/it83xx/adc.c +++ b/chip/it83xx/adc.c @@ -222,8 +222,8 @@ static void adc_init(void) * NOTE: A sample time delay (60us) also need to be included in * conversion time, so the final result is ~= 121.6us. */ - IT83XX_ADC_ADCSTS &= ~(1 << 7); - IT83XX_ADC_ADCCFG &= ~(1 << 5); + IT83XX_ADC_ADCSTS &= ~BIT(7); + IT83XX_ADC_ADCCFG &= ~BIT(5); IT83XX_ADC_ADCCTL = 1; task_waiting = TASK_ID_INVALID; diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index 75c4e1dbeb..fde5045389 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -62,11 +62,11 @@ struct clock_gate_ctrl { static void clock_module_disable(void) { /* bit0: FSPI interface tri-state */ - IT83XX_SMFI_FLHCTRL3R |= (1 << 0); + IT83XX_SMFI_FLHCTRL3R |= BIT(0); /* bit7: USB pad power-on disable */ - IT83XX_GCTRL_PMER2 &= ~(1 << 7); + IT83XX_GCTRL_PMER2 &= ~BIT(7); /* bit7: USB debug disable */ - IT83XX_GCTRL_MCCR &= ~(1 << 7); + IT83XX_GCTRL_MCCR &= ~BIT(7); clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0); clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB | CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE | @@ -146,7 +146,7 @@ void __ram_code clock_ec_pll_ctrl(enum ec_pll_ctrl mode) void __ram_code clock_pll_changed(void) { - IT83XX_GCTRL_SSCR &= ~(1 << 0); + IT83XX_GCTRL_SSCR &= ~BIT(0); /* * Update PLL settings. * Writing data to this register doesn't change the @@ -199,7 +199,7 @@ static void clock_set_pll(enum pll_freq_idx idx) * We have to set chip select pin as input mode in order to * change PLL. */ - IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | (1 << 7); + IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | BIT(7); #ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED /* * On DX version, we have to disable eSPI pad before changing @@ -281,10 +281,10 @@ void clock_init(void) clock_module_disable(); #ifdef CONFIG_HOSTCMD_X86 - IT83XX_WUC_WUESR4 = (1 << 2); + IT83XX_WUC_WUESR4 = BIT(2); task_clear_pending_irq(IT83XX_IRQ_WKINTAD); /* bit2, wake-up enable for LPC access */ - IT83XX_WUC_WUENR4 |= (1 << 2); + IT83XX_WUC_WUENR4 |= BIT(2); #endif } @@ -349,7 +349,7 @@ void clock_refresh_console_in_use(void) static void clock_event_timer_clock_change(enum ext_timer_clock_source clock, uint32_t count) { - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~(1 << 0); + IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0); IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock; IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = count; IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x3; @@ -370,7 +370,7 @@ static void clock_htimer_enable(void) static int clock_allow_low_power_idle(void) { - if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & (1 << 0))) + if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0))) return 0; if (*et_ctrl_regs[EVENT_EXT_TIMER].isr & @@ -412,7 +412,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds) chip_clear_pending_irq(i); } /* bit5: watchdog is disabled. */ - IT83XX_ETWD_ETWCTRL |= (1 << 5); + IT83XX_ETWD_ETWCTRL |= BIT(5); /* Setup GPIOs for hibernate */ if (board_hibernate_late) board_hibernate_late(); @@ -501,7 +501,7 @@ defined(CONFIG_HOSTCMD_ESPI) #ifdef CONFIG_HOSTCMD_X86 /* disable lpc access wui */ task_disable_irq(IT83XX_IRQ_WKINTAD); - IT83XX_WUC_WUESR4 = (1 << 2); + IT83XX_WUC_WUESR4 = BIT(2); task_clear_pending_irq(IT83XX_IRQ_WKINTAD); #endif /* disable uart wui */ @@ -534,7 +534,7 @@ void __idle(void) /* Check if the EC can enter deep doze mode or not */ if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) { /* reset low power mode hw timer */ - IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= (1 << 1); + IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= BIT(1); sleep_mode_t0 = get_time(); #ifdef CONFIG_HOSTCMD_X86 /* enable lpc access wui */ diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c index 38216592ad..2cdcb43f8a 100644 --- a/chip/it83xx/ec2i.c +++ b/chip/it83xx/ec2i.c @@ -160,9 +160,9 @@ enum ec2i_access { enum ec2i_status_mask { /* 1: EC read-access is still processing. */ - EC2I_STATUS_CRIB = (1 << 1), + EC2I_STATUS_CRIB = BIT(1), /* 1: EC write-access is still processing with IHD register. */ - EC2I_STATUS_CWIB = (1 << 2), + EC2I_STATUS_CWIB = BIT(2), EC2I_STATUS_ALL = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB), }; @@ -179,7 +179,7 @@ static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data) int rv = EC_ERROR_UNKNOWN; /* bit1 : VCC power on */ - if (IT83XX_SWUC_SWCTL1 & (1 << 1)) { + if (IT83XX_SWUC_SWCTL1 & BIT(1)) { /* * Wait that both CRIB and CWIB bits in IBCTL register * are cleared. @@ -191,15 +191,15 @@ static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data) /* Write the data to IHD register */ IT83XX_EC2I_IHD = data; /* Enable EC access to the PNPCFG registers */ - IT83XX_EC2I_IBMAE |= (1 << 0); + IT83XX_EC2I_IBMAE |= BIT(0); /* bit0: EC to I-Bus access enabled. */ - IT83XX_EC2I_IBCTL |= (1 << 0); + IT83XX_EC2I_IBCTL |= BIT(0); /* Wait the CWIB bit in IBCTL cleared. */ rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CWIB); /* Disable EC access to the PNPCFG registers. */ - IT83XX_EC2I_IBMAE &= ~(1 << 0); + IT83XX_EC2I_IBMAE &= ~BIT(0); /* Disable EC to I-Bus access. */ - IT83XX_EC2I_IBCTL &= ~(1 << 0); + IT83XX_EC2I_IBCTL &= ~BIT(0); } } @@ -212,7 +212,7 @@ static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel) uint8_t ihd = 0; /* bit1 : VCC power on */ - if (IT83XX_SWUC_SWCTL1 & (1 << 1)) { + if (IT83XX_SWUC_SWCTL1 & BIT(1)) { /* * Wait that both CRIB and CWIB bits in IBCTL register * are cleared. @@ -222,19 +222,19 @@ static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel) /* Set indirect host I/O offset. */ IT83XX_EC2I_IHIOA = sel; /* Enable EC access to the PNPCFG registers */ - IT83XX_EC2I_IBMAE |= (1 << 0); + IT83XX_EC2I_IBMAE |= BIT(0); /* bit1: a read-action */ - IT83XX_EC2I_IBCTL |= (1 << 1); + IT83XX_EC2I_IBCTL |= BIT(1); /* bit0: EC to I-Bus access enabled. */ - IT83XX_EC2I_IBCTL |= (1 << 0); + IT83XX_EC2I_IBCTL |= BIT(0); /* Wait the CRIB bit in IBCTL cleared. */ rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CRIB); /* Read the data from IHD register */ ihd = IT83XX_EC2I_IHD; /* Disable EC access to the PNPCFG registers. */ - IT83XX_EC2I_IBMAE &= ~(1 << 0); + IT83XX_EC2I_IBMAE &= ~BIT(0); /* Disable EC to I-Bus access. */ - IT83XX_EC2I_IBCTL &= ~(1 << 0); + IT83XX_EC2I_IBCTL &= ~BIT(0); } } diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c index 21e462596b..9e68eedf00 100644 --- a/chip/it83xx/espi.c +++ b/chip/it83xx/espi.c @@ -431,7 +431,7 @@ void __ram_code espi_fw_reset_module(void) * 01b: The VCC power status is treated as power-on. */ IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0); - IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | (1 << 6); + IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | BIT(6); } #endif @@ -457,9 +457,9 @@ static int espi_get_reset_enable_config(void) * 10b: espi_reset# is enabled on GPD2. * 11b: reset is disabled. */ - if (espi_rst->port == GPIO_D && espi_rst->mask == (1 << 2)) { + if (espi_rst->port == GPIO_D && espi_rst->mask == BIT(2)) { config = IT83XX_GPIO_GCR_LPC_RST_D2; - } else if (espi_rst->port == GPIO_B && espi_rst->mask == (1 << 7)) { + } else if (espi_rst->port == GPIO_B && espi_rst->mask == BIT(7)) { config = IT83XX_GPIO_GCR_LPC_RST_B7; } else { config = IT83XX_GPIO_GCR_LPC_RST_DISABLE; @@ -575,10 +575,10 @@ void espi_enable_pad(int enable) { if (enable) /* Enable eSPI pad. */ - IT83XX_ESPI_ESGCTRL2 &= ~(1 << 6); + IT83XX_ESPI_ESGCTRL2 &= ~BIT(6); else /* Disable eSPI pad. */ - IT83XX_ESPI_ESGCTRL2 |= (1 << 6); + IT83XX_ESPI_ESGCTRL2 |= BIT(6); } #endif @@ -593,7 +593,7 @@ void espi_init(void) * 100b: 66MHz */ #ifdef IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE - IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | (1 << 2); + IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | BIT(2); #endif /* reset vw_index_flag at initialization */ espi_reset_vw_index_flags(); @@ -602,16 +602,16 @@ void espi_init(void) * bit[3]: The reset source of PNPCFG is RSTPNP bit in RSTCH * register and WRST#. */ - IT83XX_GCTRL_RSTS &= ~(1 << 3); + IT83XX_GCTRL_RSTS &= ~BIT(3); task_clear_pending_irq(IT83XX_IRQ_ESPI_VW); /* bit7: VW interrupt enable */ - IT83XX_ESPI_VWCTRL0 |= (1 << 7); + IT83XX_ESPI_VWCTRL0 |= BIT(7); task_enable_irq(IT83XX_IRQ_ESPI_VW); /* bit7: eSPI interrupt enable */ - IT83XX_ESPI_ESGCTRL1 |= (1 << 7); + IT83XX_ESPI_ESGCTRL1 |= BIT(7); /* bit4: eSPI to WUC enable */ - IT83XX_ESPI_ESGCTRL2 |= (1 << 4); + IT83XX_ESPI_ESGCTRL2 |= BIT(4); task_enable_irq(IT83XX_IRQ_ESPI); /* enable interrupt and reset from eSPI_reset# */ diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c index f89f791f11..5c390553ef 100644 --- a/chip/it83xx/gpio.c +++ b/chip/it83xx/gpio.c @@ -100,111 +100,111 @@ static const struct { uint8_t wuc_mask; } gpio_irqs[] = { /* irq gpio_port,gpio_mask,wuc_group,wuc_mask */ - [IT83XX_IRQ_WKO20] = {GPIO_D, (1<<0), 2, (1<<0)}, - [IT83XX_IRQ_WKO21] = {GPIO_D, (1<<1), 2, (1<<1)}, - [IT83XX_IRQ_WKO22] = {GPIO_C, (1<<4), 2, (1<<2)}, - [IT83XX_IRQ_WKO23] = {GPIO_C, (1<<6), 2, (1<<3)}, - [IT83XX_IRQ_WKO24] = {GPIO_D, (1<<2), 2, (1<<4)}, + [IT83XX_IRQ_WKO20] = {GPIO_D, BIT(0), 2, BIT(0)}, + [IT83XX_IRQ_WKO21] = {GPIO_D, BIT(1), 2, BIT(1)}, + [IT83XX_IRQ_WKO22] = {GPIO_C, BIT(4), 2, BIT(2)}, + [IT83XX_IRQ_WKO23] = {GPIO_C, BIT(6), 2, BIT(3)}, + [IT83XX_IRQ_WKO24] = {GPIO_D, BIT(2), 2, BIT(4)}, #ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO40] = {GPIO_E, (1<<5), 4, (1<<0)}, - [IT83XX_IRQ_WKO45] = {GPIO_E, (1<<6), 4, (1<<5)}, - [IT83XX_IRQ_WKO46] = {GPIO_E, (1<<7), 4, (1<<6)}, + [IT83XX_IRQ_WKO40] = {GPIO_E, BIT(5), 4, BIT(0)}, + [IT83XX_IRQ_WKO45] = {GPIO_E, BIT(6), 4, BIT(5)}, + [IT83XX_IRQ_WKO46] = {GPIO_E, BIT(7), 4, BIT(6)}, #endif - [IT83XX_IRQ_WKO50] = {GPIO_K, (1<<0), 5, (1<<0)}, - [IT83XX_IRQ_WKO51] = {GPIO_K, (1<<1), 5, (1<<1)}, - [IT83XX_IRQ_WKO52] = {GPIO_K, (1<<2), 5, (1<<2)}, - [IT83XX_IRQ_WKO53] = {GPIO_K, (1<<3), 5, (1<<3)}, - [IT83XX_IRQ_WKO54] = {GPIO_K, (1<<4), 5, (1<<4)}, - [IT83XX_IRQ_WKO55] = {GPIO_K, (1<<5), 5, (1<<5)}, - [IT83XX_IRQ_WKO56] = {GPIO_K, (1<<6), 5, (1<<6)}, - [IT83XX_IRQ_WKO57] = {GPIO_K, (1<<7), 5, (1<<7)}, - [IT83XX_IRQ_WKO60] = {GPIO_H, (1<<0), 6, (1<<0)}, - [IT83XX_IRQ_WKO61] = {GPIO_H, (1<<1), 6, (1<<1)}, - [IT83XX_IRQ_WKO62] = {GPIO_H, (1<<2), 6, (1<<2)}, - [IT83XX_IRQ_WKO63] = {GPIO_H, (1<<3), 6, (1<<3)}, - [IT83XX_IRQ_WKO64] = {GPIO_F, (1<<4), 6, (1<<4)}, - [IT83XX_IRQ_WKO65] = {GPIO_F, (1<<5), 6, (1<<5)}, - [IT83XX_IRQ_WKO65] = {GPIO_F, (1<<6), 6, (1<<6)}, - [IT83XX_IRQ_WKO67] = {GPIO_F, (1<<7), 6, (1<<7)}, - [IT83XX_IRQ_WKO70] = {GPIO_E, (1<<0), 7, (1<<0)}, - [IT83XX_IRQ_WKO71] = {GPIO_E, (1<<1), 7, (1<<1)}, - [IT83XX_IRQ_WKO72] = {GPIO_E, (1<<2), 7, (1<<2)}, - [IT83XX_IRQ_WKO73] = {GPIO_E, (1<<3), 7, (1<<3)}, - [IT83XX_IRQ_WKO74] = {GPIO_I, (1<<4), 7, (1<<4)}, - [IT83XX_IRQ_WKO75] = {GPIO_I, (1<<5), 7, (1<<5)}, - [IT83XX_IRQ_WKO76] = {GPIO_I, (1<<6), 7, (1<<6)}, - [IT83XX_IRQ_WKO77] = {GPIO_I, (1<<7), 7, (1<<7)}, - [IT83XX_IRQ_WKO80] = {GPIO_A, (1<<3), 8, (1<<0)}, - [IT83XX_IRQ_WKO81] = {GPIO_A, (1<<4), 8, (1<<1)}, - [IT83XX_IRQ_WKO82] = {GPIO_A, (1<<5), 8, (1<<2)}, - [IT83XX_IRQ_WKO83] = {GPIO_A, (1<<6), 8, (1<<3)}, - [IT83XX_IRQ_WKO84] = {GPIO_B, (1<<2), 8, (1<<4)}, - [IT83XX_IRQ_WKO85] = {GPIO_C, (1<<0), 8, (1<<5)}, - [IT83XX_IRQ_WKO86] = {GPIO_C, (1<<7), 8, (1<<6)}, - [IT83XX_IRQ_WKO87] = {GPIO_D, (1<<7), 8, (1<<7)}, - [IT83XX_IRQ_WKO88] = {GPIO_H, (1<<4), 9, (1<<0)}, - [IT83XX_IRQ_WKO89] = {GPIO_H, (1<<5), 9, (1<<1)}, - [IT83XX_IRQ_WKO90] = {GPIO_H, (1<<6), 9, (1<<2)}, - [IT83XX_IRQ_WKO91] = {GPIO_A, (1<<0), 9, (1<<3)}, - [IT83XX_IRQ_WKO92] = {GPIO_A, (1<<1), 9, (1<<4)}, - [IT83XX_IRQ_WKO93] = {GPIO_A, (1<<2), 9, (1<<5)}, - [IT83XX_IRQ_WKO94] = {GPIO_B, (1<<4), 9, (1<<6)}, - [IT83XX_IRQ_WKO95] = {GPIO_C, (1<<2), 9, (1<<7)}, - [IT83XX_IRQ_WKO96] = {GPIO_F, (1<<0), 10, (1<<0)}, - [IT83XX_IRQ_WKO97] = {GPIO_F, (1<<1), 10, (1<<1)}, - [IT83XX_IRQ_WKO98] = {GPIO_F, (1<<2), 10, (1<<2)}, - [IT83XX_IRQ_WKO99] = {GPIO_F, (1<<3), 10, (1<<3)}, - [IT83XX_IRQ_WKO100] = {GPIO_A, (1<<7), 10, (1<<4)}, - [IT83XX_IRQ_WKO101] = {GPIO_B, (1<<0), 10, (1<<5)}, - [IT83XX_IRQ_WKO102] = {GPIO_B, (1<<1), 10, (1<<6)}, - [IT83XX_IRQ_WKO103] = {GPIO_B, (1<<3), 10, (1<<7)}, - [IT83XX_IRQ_WKO104] = {GPIO_B, (1<<5), 11, (1<<0)}, - [IT83XX_IRQ_WKO105] = {GPIO_B, (1<<6), 11, (1<<1)}, - [IT83XX_IRQ_WKO106] = {GPIO_B, (1<<7), 11, (1<<2)}, - [IT83XX_IRQ_WKO107] = {GPIO_C, (1<<1), 11, (1<<3)}, - [IT83XX_IRQ_WKO108] = {GPIO_C, (1<<3), 11, (1<<4)}, - [IT83XX_IRQ_WKO109] = {GPIO_C, (1<<5), 11, (1<<5)}, - [IT83XX_IRQ_WKO110] = {GPIO_D, (1<<3), 11, (1<<6)}, - [IT83XX_IRQ_WKO111] = {GPIO_D, (1<<4), 11, (1<<7)}, - [IT83XX_IRQ_WKO112] = {GPIO_D, (1<<5), 12, (1<<0)}, - [IT83XX_IRQ_WKO113] = {GPIO_D, (1<<6), 12, (1<<1)}, - [IT83XX_IRQ_WKO114] = {GPIO_E, (1<<4), 12, (1<<2)}, - [IT83XX_IRQ_WKO115] = {GPIO_G, (1<<0), 12, (1<<3)}, - [IT83XX_IRQ_WKO116] = {GPIO_G, (1<<1), 12, (1<<4)}, - [IT83XX_IRQ_WKO117] = {GPIO_G, (1<<2), 12, (1<<5)}, - [IT83XX_IRQ_WKO118] = {GPIO_G, (1<<6), 12, (1<<6)}, - [IT83XX_IRQ_WKO119] = {GPIO_I, (1<<0), 12, (1<<7)}, - [IT83XX_IRQ_WKO120] = {GPIO_I, (1<<1), 13, (1<<0)}, - [IT83XX_IRQ_WKO121] = {GPIO_I, (1<<2), 13, (1<<1)}, - [IT83XX_IRQ_WKO122] = {GPIO_I, (1<<3), 13, (1<<2)}, + [IT83XX_IRQ_WKO50] = {GPIO_K, BIT(0), 5, BIT(0)}, + [IT83XX_IRQ_WKO51] = {GPIO_K, BIT(1), 5, BIT(1)}, + [IT83XX_IRQ_WKO52] = {GPIO_K, BIT(2), 5, BIT(2)}, + [IT83XX_IRQ_WKO53] = {GPIO_K, BIT(3), 5, BIT(3)}, + [IT83XX_IRQ_WKO54] = {GPIO_K, BIT(4), 5, BIT(4)}, + [IT83XX_IRQ_WKO55] = {GPIO_K, BIT(5), 5, BIT(5)}, + [IT83XX_IRQ_WKO56] = {GPIO_K, BIT(6), 5, BIT(6)}, + [IT83XX_IRQ_WKO57] = {GPIO_K, BIT(7), 5, BIT(7)}, + [IT83XX_IRQ_WKO60] = {GPIO_H, BIT(0), 6, BIT(0)}, + [IT83XX_IRQ_WKO61] = {GPIO_H, BIT(1), 6, BIT(1)}, + [IT83XX_IRQ_WKO62] = {GPIO_H, BIT(2), 6, BIT(2)}, + [IT83XX_IRQ_WKO63] = {GPIO_H, BIT(3), 6, BIT(3)}, + [IT83XX_IRQ_WKO64] = {GPIO_F, BIT(4), 6, BIT(4)}, + [IT83XX_IRQ_WKO65] = {GPIO_F, BIT(5), 6, BIT(5)}, + [IT83XX_IRQ_WKO65] = {GPIO_F, BIT(6), 6, BIT(6)}, + [IT83XX_IRQ_WKO67] = {GPIO_F, BIT(7), 6, BIT(7)}, + [IT83XX_IRQ_WKO70] = {GPIO_E, BIT(0), 7, BIT(0)}, + [IT83XX_IRQ_WKO71] = {GPIO_E, BIT(1), 7, BIT(1)}, + [IT83XX_IRQ_WKO72] = {GPIO_E, BIT(2), 7, BIT(2)}, + [IT83XX_IRQ_WKO73] = {GPIO_E, BIT(3), 7, BIT(3)}, + [IT83XX_IRQ_WKO74] = {GPIO_I, BIT(4), 7, BIT(4)}, + [IT83XX_IRQ_WKO75] = {GPIO_I, BIT(5), 7, BIT(5)}, + [IT83XX_IRQ_WKO76] = {GPIO_I, BIT(6), 7, BIT(6)}, + [IT83XX_IRQ_WKO77] = {GPIO_I, BIT(7), 7, BIT(7)}, + [IT83XX_IRQ_WKO80] = {GPIO_A, BIT(3), 8, BIT(0)}, + [IT83XX_IRQ_WKO81] = {GPIO_A, BIT(4), 8, BIT(1)}, + [IT83XX_IRQ_WKO82] = {GPIO_A, BIT(5), 8, BIT(2)}, + [IT83XX_IRQ_WKO83] = {GPIO_A, BIT(6), 8, BIT(3)}, + [IT83XX_IRQ_WKO84] = {GPIO_B, BIT(2), 8, BIT(4)}, + [IT83XX_IRQ_WKO85] = {GPIO_C, BIT(0), 8, BIT(5)}, + [IT83XX_IRQ_WKO86] = {GPIO_C, BIT(7), 8, BIT(6)}, + [IT83XX_IRQ_WKO87] = {GPIO_D, BIT(7), 8, BIT(7)}, + [IT83XX_IRQ_WKO88] = {GPIO_H, BIT(4), 9, BIT(0)}, + [IT83XX_IRQ_WKO89] = {GPIO_H, BIT(5), 9, BIT(1)}, + [IT83XX_IRQ_WKO90] = {GPIO_H, BIT(6), 9, BIT(2)}, + [IT83XX_IRQ_WKO91] = {GPIO_A, BIT(0), 9, BIT(3)}, + [IT83XX_IRQ_WKO92] = {GPIO_A, BIT(1), 9, BIT(4)}, + [IT83XX_IRQ_WKO93] = {GPIO_A, BIT(2), 9, BIT(5)}, + [IT83XX_IRQ_WKO94] = {GPIO_B, BIT(4), 9, BIT(6)}, + [IT83XX_IRQ_WKO95] = {GPIO_C, BIT(2), 9, BIT(7)}, + [IT83XX_IRQ_WKO96] = {GPIO_F, BIT(0), 10, BIT(0)}, + [IT83XX_IRQ_WKO97] = {GPIO_F, BIT(1), 10, BIT(1)}, + [IT83XX_IRQ_WKO98] = {GPIO_F, BIT(2), 10, BIT(2)}, + [IT83XX_IRQ_WKO99] = {GPIO_F, BIT(3), 10, BIT(3)}, + [IT83XX_IRQ_WKO100] = {GPIO_A, BIT(7), 10, BIT(4)}, + [IT83XX_IRQ_WKO101] = {GPIO_B, BIT(0), 10, BIT(5)}, + [IT83XX_IRQ_WKO102] = {GPIO_B, BIT(1), 10, BIT(6)}, + [IT83XX_IRQ_WKO103] = {GPIO_B, BIT(3), 10, BIT(7)}, + [IT83XX_IRQ_WKO104] = {GPIO_B, BIT(5), 11, BIT(0)}, + [IT83XX_IRQ_WKO105] = {GPIO_B, BIT(6), 11, BIT(1)}, + [IT83XX_IRQ_WKO106] = {GPIO_B, BIT(7), 11, BIT(2)}, + [IT83XX_IRQ_WKO107] = {GPIO_C, BIT(1), 11, BIT(3)}, + [IT83XX_IRQ_WKO108] = {GPIO_C, BIT(3), 11, BIT(4)}, + [IT83XX_IRQ_WKO109] = {GPIO_C, BIT(5), 11, BIT(5)}, + [IT83XX_IRQ_WKO110] = {GPIO_D, BIT(3), 11, BIT(6)}, + [IT83XX_IRQ_WKO111] = {GPIO_D, BIT(4), 11, BIT(7)}, + [IT83XX_IRQ_WKO112] = {GPIO_D, BIT(5), 12, BIT(0)}, + [IT83XX_IRQ_WKO113] = {GPIO_D, BIT(6), 12, BIT(1)}, + [IT83XX_IRQ_WKO114] = {GPIO_E, BIT(4), 12, BIT(2)}, + [IT83XX_IRQ_WKO115] = {GPIO_G, BIT(0), 12, BIT(3)}, + [IT83XX_IRQ_WKO116] = {GPIO_G, BIT(1), 12, BIT(4)}, + [IT83XX_IRQ_WKO117] = {GPIO_G, BIT(2), 12, BIT(5)}, + [IT83XX_IRQ_WKO118] = {GPIO_G, BIT(6), 12, BIT(6)}, + [IT83XX_IRQ_WKO119] = {GPIO_I, BIT(0), 12, BIT(7)}, + [IT83XX_IRQ_WKO120] = {GPIO_I, BIT(1), 13, BIT(0)}, + [IT83XX_IRQ_WKO121] = {GPIO_I, BIT(2), 13, BIT(1)}, + [IT83XX_IRQ_WKO122] = {GPIO_I, BIT(3), 13, BIT(2)}, #ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO123] = {GPIO_G, (1<<3), 13, (1<<3)}, - [IT83XX_IRQ_WKO124] = {GPIO_G, (1<<4), 13, (1<<4)}, - [IT83XX_IRQ_WKO125] = {GPIO_G, (1<<5), 13, (1<<5)}, - [IT83XX_IRQ_WKO126] = {GPIO_G, (1<<7), 13, (1<<6)}, + [IT83XX_IRQ_WKO123] = {GPIO_G, BIT(3), 13, BIT(3)}, + [IT83XX_IRQ_WKO124] = {GPIO_G, BIT(4), 13, BIT(4)}, + [IT83XX_IRQ_WKO125] = {GPIO_G, BIT(5), 13, BIT(5)}, + [IT83XX_IRQ_WKO126] = {GPIO_G, BIT(7), 13, BIT(6)}, #endif - [IT83XX_IRQ_WKO128] = {GPIO_J, (1<<0), 14, (1<<0)}, - [IT83XX_IRQ_WKO129] = {GPIO_J, (1<<1), 14, (1<<1)}, - [IT83XX_IRQ_WKO130] = {GPIO_J, (1<<2), 14, (1<<2)}, - [IT83XX_IRQ_WKO131] = {GPIO_J, (1<<3), 14, (1<<3)}, - [IT83XX_IRQ_WKO132] = {GPIO_J, (1<<4), 14, (1<<4)}, - [IT83XX_IRQ_WKO133] = {GPIO_J, (1<<5), 14, (1<<5)}, - [IT83XX_IRQ_WKO136] = {GPIO_L, (1<<0), 15, (1<<0)}, - [IT83XX_IRQ_WKO137] = {GPIO_L, (1<<1), 15, (1<<1)}, - [IT83XX_IRQ_WKO138] = {GPIO_L, (1<<2), 15, (1<<2)}, - [IT83XX_IRQ_WKO139] = {GPIO_L, (1<<3), 15, (1<<3)}, - [IT83XX_IRQ_WKO140] = {GPIO_L, (1<<4), 15, (1<<4)}, - [IT83XX_IRQ_WKO141] = {GPIO_L, (1<<5), 15, (1<<5)}, - [IT83XX_IRQ_WKO142] = {GPIO_L, (1<<6), 15, (1<<6)}, - [IT83XX_IRQ_WKO143] = {GPIO_L, (1<<7), 15, (1<<7)}, + [IT83XX_IRQ_WKO128] = {GPIO_J, BIT(0), 14, BIT(0)}, + [IT83XX_IRQ_WKO129] = {GPIO_J, BIT(1), 14, BIT(1)}, + [IT83XX_IRQ_WKO130] = {GPIO_J, BIT(2), 14, BIT(2)}, + [IT83XX_IRQ_WKO131] = {GPIO_J, BIT(3), 14, BIT(3)}, + [IT83XX_IRQ_WKO132] = {GPIO_J, BIT(4), 14, BIT(4)}, + [IT83XX_IRQ_WKO133] = {GPIO_J, BIT(5), 14, BIT(5)}, + [IT83XX_IRQ_WKO136] = {GPIO_L, BIT(0), 15, BIT(0)}, + [IT83XX_IRQ_WKO137] = {GPIO_L, BIT(1), 15, BIT(1)}, + [IT83XX_IRQ_WKO138] = {GPIO_L, BIT(2), 15, BIT(2)}, + [IT83XX_IRQ_WKO139] = {GPIO_L, BIT(3), 15, BIT(3)}, + [IT83XX_IRQ_WKO140] = {GPIO_L, BIT(4), 15, BIT(4)}, + [IT83XX_IRQ_WKO141] = {GPIO_L, BIT(5), 15, BIT(5)}, + [IT83XX_IRQ_WKO142] = {GPIO_L, BIT(6), 15, BIT(6)}, + [IT83XX_IRQ_WKO143] = {GPIO_L, BIT(7), 15, BIT(7)}, #ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO144] = {GPIO_M, (1<<0), 16, (1<<0)}, - [IT83XX_IRQ_WKO145] = {GPIO_M, (1<<1), 16, (1<<1)}, - [IT83XX_IRQ_WKO146] = {GPIO_M, (1<<2), 16, (1<<2)}, - [IT83XX_IRQ_WKO147] = {GPIO_M, (1<<3), 16, (1<<3)}, - [IT83XX_IRQ_WKO148] = {GPIO_M, (1<<4), 16, (1<<4)}, - [IT83XX_IRQ_WKO149] = {GPIO_M, (1<<5), 16, (1<<5)}, - [IT83XX_IRQ_WKO150] = {GPIO_M, (1<<6), 16, (1<<6)}, + [IT83XX_IRQ_WKO144] = {GPIO_M, BIT(0), 16, BIT(0)}, + [IT83XX_IRQ_WKO145] = {GPIO_M, BIT(1), 16, BIT(1)}, + [IT83XX_IRQ_WKO146] = {GPIO_M, BIT(2), 16, BIT(2)}, + [IT83XX_IRQ_WKO147] = {GPIO_M, BIT(3), 16, BIT(3)}, + [IT83XX_IRQ_WKO148] = {GPIO_M, BIT(4), 16, BIT(4)}, + [IT83XX_IRQ_WKO149] = {GPIO_M, BIT(5), 16, BIT(5)}, + [IT83XX_IRQ_WKO150] = {GPIO_M, BIT(6), 16, BIT(6)}, #endif [IT83XX_IRQ_COUNT-1] = {0, 0, 0, 0}, }; @@ -238,119 +238,119 @@ struct gpio_1p8v_t { static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = { #ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED - [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC24, (1 << 1)}, - [6] = {&IT83XX_GPIO_GRC24, (1 << 5)}, - [7] = {&IT83XX_GPIO_GRC24, (1 << 6)} }, - [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, (1 << 1)}, - [4] = {&IT83XX_GPIO_GRC22, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC19, (1 << 7)}, - [6] = {&IT83XX_GPIO_GRC19, (1 << 6)}, - [7] = {&IT83XX_GPIO_GRC24, (1 << 4)} }, - [GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, (1 << 7)}, - [1] = {&IT83XX_GPIO_GRC19, (1 << 5)}, - [2] = {&IT83XX_GPIO_GRC19, (1 << 4)}, - [4] = {&IT83XX_GPIO_GRC24, (1 << 2)}, - [6] = {&IT83XX_GPIO_GRC24, (1 << 3)}, - [7] = {&IT83XX_GPIO_GRC19, (1 << 3)} }, - [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, (1 << 2)}, - [1] = {&IT83XX_GPIO_GRC19, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC19, (1 << 0)}, - [3] = {&IT83XX_GPIO_GRC20, (1 << 7)}, - [4] = {&IT83XX_GPIO_GRC20, (1 << 6)}, - [5] = {&IT83XX_GPIO_GRC22, (1 << 4)}, - [6] = {&IT83XX_GPIO_GRC22, (1 << 5)}, - [7] = {&IT83XX_GPIO_GRC22, (1 << 6)} }, - [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, (1 << 5)}, - [1] = {&IT83XX_GPIO_GCR28, (1 << 6)}, - [2] = {&IT83XX_GPIO_GCR28, (1 << 7)}, - [4] = {&IT83XX_GPIO_GRC22, (1 << 2)}, - [5] = {&IT83XX_GPIO_GRC22, (1 << 3)}, - [6] = {&IT83XX_GPIO_GRC20, (1 << 4)}, - [7] = {&IT83XX_GPIO_GRC20, (1 << 3)} }, - [GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, (1 << 4)}, - [1] = {&IT83XX_GPIO_GCR28, (1 << 5)}, - [2] = {&IT83XX_GPIO_GRC20, (1 << 2)}, - [3] = {&IT83XX_GPIO_GRC20, (1 << 1)}, - [4] = {&IT83XX_GPIO_GRC20, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC21, (1 << 7)}, - [6] = {&IT83XX_GPIO_GRC21, (1 << 6)}, - [7] = {&IT83XX_GPIO_GRC21, (1 << 5)} }, - [GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, (1 << 2)}, - [1] = {&IT83XX_GPIO_GRC21, (1 << 4)}, - [2] = {&IT83XX_GPIO_GCR28, (1 << 3)}, - [6] = {&IT83XX_GPIO_GRC21, (1 << 3)} }, - [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, (1 << 2)}, - [1] = {&IT83XX_GPIO_GRC21, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC21, (1 << 0)}, - [5] = {&IT83XX_GPIO_GCR27, (1 << 7)}, - [6] = {&IT83XX_GPIO_GCR28, (1 << 0)} }, - [GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, (1 << 3)}, - [1] = {&IT83XX_GPIO_GRC23, (1 << 4)}, - [2] = {&IT83XX_GPIO_GRC23, (1 << 5)}, - [3] = {&IT83XX_GPIO_GRC23, (1 << 6)}, - [4] = {&IT83XX_GPIO_GRC23, (1 << 7)}, - [5] = {&IT83XX_GPIO_GCR27, (1 << 4)}, - [6] = {&IT83XX_GPIO_GCR27, (1 << 5)}, - [7] = {&IT83XX_GPIO_GCR27, (1 << 6)} }, - [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, (1 << 0)}, - [1] = {&IT83XX_GPIO_GRC23, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC23, (1 << 2)}, - [3] = {&IT83XX_GPIO_GRC23, (1 << 3)}, - [4] = {&IT83XX_GPIO_GCR27, (1 << 0)}, - [5] = {&IT83XX_GPIO_GCR27, (1 << 1)}, - [6] = {&IT83XX_GPIO_GCR27, (1 << 2)} }, - [GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, (1 << 0)}, - [1] = {&IT83XX_GPIO_GCR26, (1 << 1)}, - [2] = {&IT83XX_GPIO_GCR26, (1 << 2)}, - [3] = {&IT83XX_GPIO_GCR26, (1 << 3)}, - [4] = {&IT83XX_GPIO_GCR26, (1 << 4)}, - [5] = {&IT83XX_GPIO_GCR26, (1 << 5)}, - [6] = {&IT83XX_GPIO_GCR26, (1 << 6)}, - [7] = {&IT83XX_GPIO_GCR26, (1 << 7)} }, - [GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, (1 << 0)}, - [1] = {&IT83XX_GPIO_GCR25, (1 << 1)}, - [2] = {&IT83XX_GPIO_GCR25, (1 << 2)}, - [3] = {&IT83XX_GPIO_GCR25, (1 << 3)}, - [4] = {&IT83XX_GPIO_GCR25, (1 << 4)}, - [5] = {&IT83XX_GPIO_GCR25, (1 << 5)}, - [6] = {&IT83XX_GPIO_GCR25, (1 << 6)}, - [7] = {&IT83XX_GPIO_GCR25, (1 << 7)} }, + [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC24, BIT(1)}, + [6] = {&IT83XX_GPIO_GRC24, BIT(5)}, + [7] = {&IT83XX_GPIO_GRC24, BIT(6)} }, + [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)}, + [4] = {&IT83XX_GPIO_GRC22, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC19, BIT(7)}, + [6] = {&IT83XX_GPIO_GRC19, BIT(6)}, + [7] = {&IT83XX_GPIO_GRC24, BIT(4)} }, + [GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, BIT(7)}, + [1] = {&IT83XX_GPIO_GRC19, BIT(5)}, + [2] = {&IT83XX_GPIO_GRC19, BIT(4)}, + [4] = {&IT83XX_GPIO_GRC24, BIT(2)}, + [6] = {&IT83XX_GPIO_GRC24, BIT(3)}, + [7] = {&IT83XX_GPIO_GRC19, BIT(3)} }, + [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)}, + [1] = {&IT83XX_GPIO_GRC19, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC19, BIT(0)}, + [3] = {&IT83XX_GPIO_GRC20, BIT(7)}, + [4] = {&IT83XX_GPIO_GRC20, BIT(6)}, + [5] = {&IT83XX_GPIO_GRC22, BIT(4)}, + [6] = {&IT83XX_GPIO_GRC22, BIT(5)}, + [7] = {&IT83XX_GPIO_GRC22, BIT(6)} }, + [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)}, + [1] = {&IT83XX_GPIO_GCR28, BIT(6)}, + [2] = {&IT83XX_GPIO_GCR28, BIT(7)}, + [4] = {&IT83XX_GPIO_GRC22, BIT(2)}, + [5] = {&IT83XX_GPIO_GRC22, BIT(3)}, + [6] = {&IT83XX_GPIO_GRC20, BIT(4)}, + [7] = {&IT83XX_GPIO_GRC20, BIT(3)} }, + [GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, BIT(4)}, + [1] = {&IT83XX_GPIO_GCR28, BIT(5)}, + [2] = {&IT83XX_GPIO_GRC20, BIT(2)}, + [3] = {&IT83XX_GPIO_GRC20, BIT(1)}, + [4] = {&IT83XX_GPIO_GRC20, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC21, BIT(7)}, + [6] = {&IT83XX_GPIO_GRC21, BIT(6)}, + [7] = {&IT83XX_GPIO_GRC21, BIT(5)} }, + [GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, BIT(2)}, + [1] = {&IT83XX_GPIO_GRC21, BIT(4)}, + [2] = {&IT83XX_GPIO_GCR28, BIT(3)}, + [6] = {&IT83XX_GPIO_GRC21, BIT(3)} }, + [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)}, + [1] = {&IT83XX_GPIO_GRC21, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC21, BIT(0)}, + [5] = {&IT83XX_GPIO_GCR27, BIT(7)}, + [6] = {&IT83XX_GPIO_GCR28, BIT(0)} }, + [GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, BIT(3)}, + [1] = {&IT83XX_GPIO_GRC23, BIT(4)}, + [2] = {&IT83XX_GPIO_GRC23, BIT(5)}, + [3] = {&IT83XX_GPIO_GRC23, BIT(6)}, + [4] = {&IT83XX_GPIO_GRC23, BIT(7)}, + [5] = {&IT83XX_GPIO_GCR27, BIT(4)}, + [6] = {&IT83XX_GPIO_GCR27, BIT(5)}, + [7] = {&IT83XX_GPIO_GCR27, BIT(6)} }, + [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)}, + [1] = {&IT83XX_GPIO_GRC23, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC23, BIT(2)}, + [3] = {&IT83XX_GPIO_GRC23, BIT(3)}, + [4] = {&IT83XX_GPIO_GCR27, BIT(0)}, + [5] = {&IT83XX_GPIO_GCR27, BIT(1)}, + [6] = {&IT83XX_GPIO_GCR27, BIT(2)} }, + [GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, BIT(0)}, + [1] = {&IT83XX_GPIO_GCR26, BIT(1)}, + [2] = {&IT83XX_GPIO_GCR26, BIT(2)}, + [3] = {&IT83XX_GPIO_GCR26, BIT(3)}, + [4] = {&IT83XX_GPIO_GCR26, BIT(4)}, + [5] = {&IT83XX_GPIO_GCR26, BIT(5)}, + [6] = {&IT83XX_GPIO_GCR26, BIT(6)}, + [7] = {&IT83XX_GPIO_GCR26, BIT(7)} }, + [GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, BIT(0)}, + [1] = {&IT83XX_GPIO_GCR25, BIT(1)}, + [2] = {&IT83XX_GPIO_GCR25, BIT(2)}, + [3] = {&IT83XX_GPIO_GCR25, BIT(3)}, + [4] = {&IT83XX_GPIO_GCR25, BIT(4)}, + [5] = {&IT83XX_GPIO_GCR25, BIT(5)}, + [6] = {&IT83XX_GPIO_GCR25, BIT(6)}, + [7] = {&IT83XX_GPIO_GCR25, BIT(7)} }, #else - [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC24, (1 << 1)} }, - [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, (1 << 1)}, - [4] = {&IT83XX_GPIO_GRC22, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC19, (1 << 7)}, - [6] = {&IT83XX_GPIO_GRC19, (1 << 6)} }, - [GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, (1 << 5)}, - [2] = {&IT83XX_GPIO_GRC19, (1 << 4)}, - [7] = {&IT83XX_GPIO_GRC19, (1 << 3)} }, - [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, (1 << 2)}, - [1] = {&IT83XX_GPIO_GRC19, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC19, (1 << 0)}, - [3] = {&IT83XX_GPIO_GRC20, (1 << 7)}, - [4] = {&IT83XX_GPIO_GRC20, (1 << 6)} }, - [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, (1 << 5)}, - [6] = {&IT83XX_GPIO_GRC20, (1 << 4)}, - [7] = {&IT83XX_GPIO_GRC20, (1 << 3)} }, - [GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, (1 << 2)}, - [3] = {&IT83XX_GPIO_GRC20, (1 << 1)}, - [4] = {&IT83XX_GPIO_GRC20, (1 << 0)}, - [5] = {&IT83XX_GPIO_GRC21, (1 << 7)}, - [6] = {&IT83XX_GPIO_GRC21, (1 << 6)}, - [7] = {&IT83XX_GPIO_GRC21, (1 << 5)} }, - [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, (1 << 2)}, - [1] = {&IT83XX_GPIO_GRC21, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC21, (1 << 0)} }, - [GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, (1 << 4)}, - [2] = {&IT83XX_GPIO_GRC23, (1 << 5)}, - [3] = {&IT83XX_GPIO_GRC23, (1 << 6)}, - [4] = {&IT83XX_GPIO_GRC23, (1 << 7)} }, - [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, (1 << 0)}, - [1] = {&IT83XX_GPIO_GRC23, (1 << 1)}, - [2] = {&IT83XX_GPIO_GRC23, (1 << 2)}, - [3] = {&IT83XX_GPIO_GRC23, (1 << 3)} }, + [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC24, BIT(1)} }, + [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)}, + [4] = {&IT83XX_GPIO_GRC22, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC19, BIT(7)}, + [6] = {&IT83XX_GPIO_GRC19, BIT(6)} }, + [GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, BIT(5)}, + [2] = {&IT83XX_GPIO_GRC19, BIT(4)}, + [7] = {&IT83XX_GPIO_GRC19, BIT(3)} }, + [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)}, + [1] = {&IT83XX_GPIO_GRC19, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC19, BIT(0)}, + [3] = {&IT83XX_GPIO_GRC20, BIT(7)}, + [4] = {&IT83XX_GPIO_GRC20, BIT(6)} }, + [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)}, + [6] = {&IT83XX_GPIO_GRC20, BIT(4)}, + [7] = {&IT83XX_GPIO_GRC20, BIT(3)} }, + [GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, BIT(2)}, + [3] = {&IT83XX_GPIO_GRC20, BIT(1)}, + [4] = {&IT83XX_GPIO_GRC20, BIT(0)}, + [5] = {&IT83XX_GPIO_GRC21, BIT(7)}, + [6] = {&IT83XX_GPIO_GRC21, BIT(6)}, + [7] = {&IT83XX_GPIO_GRC21, BIT(5)} }, + [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)}, + [1] = {&IT83XX_GPIO_GRC21, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC21, BIT(0)} }, + [GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, BIT(4)}, + [2] = {&IT83XX_GPIO_GRC23, BIT(5)}, + [3] = {&IT83XX_GPIO_GRC23, BIT(6)}, + [4] = {&IT83XX_GPIO_GRC23, BIT(7)} }, + [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)}, + [1] = {&IT83XX_GPIO_GRC23, BIT(1)}, + [2] = {&IT83XX_GPIO_GRC23, BIT(2)}, + [3] = {&IT83XX_GPIO_GRC23, BIT(3)} }, #endif }; diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c index e65fea38fa..ecfbcf7be6 100644 --- a/chip/it83xx/hwtimer.c +++ b/chip/it83xx/hwtimer.c @@ -81,7 +81,7 @@ static void free_run_timer_overflow(void) /* set timer counter register */ IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff; /* bit[1], timer reset */ - IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 1); + IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1); } /* w/c interrupt status */ task_clear_pending_irq(et_ctrl_regs[FREE_EXT_TIMER_H].irq); @@ -114,14 +114,14 @@ void __hw_clock_source_set(uint32_t ts) /* counting down timer, microseconds to timer counter register */ IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff - ts; /* bit[1], timer reset */ - IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 1); + IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1); } void __hw_clock_event_set(uint32_t deadline) { uint32_t wait; /* bit0, disable event timer */ - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~(1 << 0); + IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0); /* w/c interrupt status */ event_timer_clear_pending_isr(); /* microseconds to timer counter */ @@ -139,7 +139,7 @@ uint32_t __hw_clock_event_get(void) uint32_t next_event_us = __hw_clock_source_read(); /* bit0, event timer is enabled */ - if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & (1 << 0)) { + if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)) { /* timer counter observation value to microseconds */ next_event_us += EVENT_TIMER_COUNT_TO_US( #ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES @@ -161,7 +161,7 @@ void __hw_clock_event_clear(void) int __hw_clock_source_init(uint32_t start_t) { /* bit3, timer 3 and timer 4 combinational mode */ - IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 3); + IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(3); /* init free running timer (timer 4, TIMER_H), clock source is 8mhz */ ext_timer_ms(FREE_EXT_TIMER_H, EXT_PSR_8M_HZ, 0, 1, 0xffffffff, 1, 1); /* 1us counter setting (timer 3, TIMER_L) */ @@ -181,7 +181,7 @@ static void __hw_clock_source_irq(void) /* SW/HW interrupt of event timer. */ if (irq == et_ctrl_regs[EVENT_EXT_TIMER].irq) { IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = 0xffffffff; - IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= (1 << 1); + IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= BIT(1); event_timer_clear_pending_isr(); process_timers(0); return; diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c index a88599b380..56f805b9f6 100644 --- a/chip/it83xx/i2c.c +++ b/chip/it83xx/i2c.c @@ -292,7 +292,7 @@ static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct, if (first_byte) { /* First byte must be slave address. */ IT83XX_I2C_DTR(p_ch) = - data | (direct == RX_DIRECT ? (1 << 0) : 0); + data | (direct == RX_DIRECT ? BIT(0) : 0); /* start or repeat start signal. */ IT83XX_I2C_CTR(p_ch) = E_START_ID; } else { @@ -457,7 +457,7 @@ static void enhanced_i2c_start(int p) */ IT83XX_I2C_TOR(p_ch) = I2C_CLK_LOW_TIMEOUT; /* bit1: Enable enhanced i2c module */ - IT83XX_I2C_CTR1(p_ch) = (1 << 1); + IT83XX_I2C_CTR1(p_ch) = BIT(1); } static int enhanced_i2c_tran_write(int p) diff --git a/chip/it83xx/keyboard_raw.c b/chip/it83xx/keyboard_raw.c index 9c5d1028ae..d6d01e1247 100644 --- a/chip/it83xx/keyboard_raw.c +++ b/chip/it83xx/keyboard_raw.c @@ -31,7 +31,7 @@ void keyboard_raw_init(void) #ifdef CONFIG_KEYBOARD_COL2_INVERTED /* KSO[2] is high, others are low. */ - IT83XX_KBS_KSOL = (1 << 2); + IT83XX_KBS_KSOL = BIT(2); #else /* KSO[7:0] pins low. */ IT83XX_KBS_KSOL = 0x00; @@ -81,7 +81,7 @@ test_mockable void keyboard_raw_drive_column(int col) #ifdef CONFIG_KEYBOARD_COL2_INVERTED /* KSO[2] is inverted. */ - mask ^= (1 << 2); + mask ^= BIT(2); #endif IT83XX_KBS_KSOL = mask & 0xff; IT83XX_KBS_KSOH1 = (mask >> 8) & 0xff; diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c index 5765788718..5ca7cf91b9 100644 --- a/chip/it83xx/lpc.c +++ b/chip/it83xx/lpc.c @@ -103,7 +103,7 @@ static void pm_put_data_out(enum lpc_pm_ch ch, uint8_t out) static void pm_clear_ibf(enum lpc_pm_ch ch) { /* bit7, write-1 clear IBF */ - IT83XX_PMC_PMIE(ch) |= (1 << 7); + IT83XX_PMC_PMIE(ch) |= BIT(7); } #ifdef CONFIG_KEYBOARD_IRQ_GPIO @@ -340,8 +340,8 @@ void lpc_keyboard_clear_buffer(void) uint32_t int_mask = get_int_mask(); interrupt_disable(); /* bit6, write-1 clear OBF */ - IT83XX_KBC_KBHICR |= (1 << 6); - IT83XX_KBC_KBHICR &= ~(1 << 6); + IT83XX_KBC_KBHICR |= BIT(6); + IT83XX_KBC_KBHICR &= ~BIT(6); set_int_mask(int_mask); } @@ -392,8 +392,8 @@ void lpc_kbc_ibf_interrupt(void) keyboard_host_write(IT83XX_KBC_KBHIDIR, (IT83XX_KBC_KBHISR & 0x08) ? 1 : 0); /* bit7, write-1 clear IBF */ - IT83XX_KBC_KBHICR |= (1 << 7); - IT83XX_KBC_KBHICR &= ~(1 << 7); + IT83XX_KBC_KBHICR |= BIT(7); + IT83XX_KBC_KBHICR &= ~BIT(7); } task_clear_pending_irq(IT83XX_IRQ_KBC_IN); @@ -745,7 +745,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 8d2d8016bb..6414ec9d16 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1179,26 +1179,26 @@ enum i2c_channels { #define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port))) #define IT83XX_USBPD_GCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0) -#define USBPD_REG_MASK_SW_RESET_BIT (1 << 7) -#define USBPD_REG_MASK_TYPE_C_DETECT_RESET (1 << 6) -#define USBPD_REG_MASK_BMC_PHY (1 << 4) -#define USBPD_REG_MASK_AUTO_SEND_SW_RESET (1 << 3) -#define USBPD_REG_MASK_AUTO_SEND_HW_RESET (1 << 2) -#define USBPD_REG_MASK_SNIFFER_MODE (1 << 1) -#define USBPD_REG_MASK_GLOBAL_ENABLE (1 << 0) +#define USBPD_REG_MASK_SW_RESET_BIT BIT(7) +#define USBPD_REG_MASK_TYPE_C_DETECT_RESET BIT(6) +#define USBPD_REG_MASK_BMC_PHY BIT(4) +#define USBPD_REG_MASK_AUTO_SEND_SW_RESET BIT(3) +#define USBPD_REG_MASK_AUTO_SEND_HW_RESET BIT(2) +#define USBPD_REG_MASK_SNIFFER_MODE BIT(1) +#define USBPD_REG_MASK_GLOBAL_ENABLE BIT(0) #define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p)+0x01) -#define USBPD_REG_MASK_SOPPP_ENABLE (1 << 7) -#define USBPD_REG_MASK_SOPP_ENABLE (1 << 6) -#define USBPD_REG_MASK_SOP_ENABLE (1 << 5) +#define USBPD_REG_MASK_SOPPP_ENABLE BIT(7) +#define USBPD_REG_MASK_SOPP_ENABLE BIT(6) +#define USBPD_REG_MASK_SOP_ENABLE BIT(5) #define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p)+0x04) -#define USBPD_REG_MASK_DISABLE_CC (1 << 4) +#define USBPD_REG_MASK_DISABLE_CC BIT(4) #define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x05) #ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT -#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT ((1 << 3) | (1 << 1)) -#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT ((1 << 7) | (1 << 5)) +#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT (BIT(3) | BIT(1)) +#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT (BIT(7) | BIT(5)) #else -#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT (1 << 3) -#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT (1 << 7) +#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT BIT(3) +#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT BIT(7) #endif #define USBPD_CC1_DISCONNECTED(p) \ ((IT83XX_USBPD_CCCSR(p) | IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) & \ @@ -1208,35 +1208,35 @@ enum i2c_channels { ~IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) #define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p)+0x06) -#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 (1 << 5) -#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 (1 << 1) +#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5) +#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1) #define IT83XX_USBPD_DFPVDR(p) REG8(IT83XX_USBPD_BASE(p)+0x08) #define IT83XX_USBPD_UFPVDR(p) REG8(IT83XX_USBPD_BASE(p)+0x09) #define IT83XX_USBPD_CCADCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0C) #define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p)+0x14) -#define USBPD_REG_MASK_TYPE_C_DETECT (1 << 7) -#define USBPD_REG_MASK_CABLE_RESET_DETECT (1 << 6) -#define USBPD_REG_MASK_HARD_RESET_DETECT (1 << 5) -#define USBPD_REG_MASK_MSG_RX_DONE (1 << 4) -#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE (1 << 3) -#define USBPD_REG_MASK_HARD_RESET_TX_DONE (1 << 2) -#define USBPD_REG_MASK_MSG_TX_DONE (1 << 1) -#define USBPD_REG_MASK_TIMER_TIMEOUT (1 << 0) +#define USBPD_REG_MASK_TYPE_C_DETECT BIT(7) +#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6) +#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5) +#define USBPD_REG_MASK_MSG_RX_DONE BIT(4) +#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3) +#define USBPD_REG_MASK_HARD_RESET_TX_DONE BIT(2) +#define USBPD_REG_MASK_MSG_TX_DONE BIT(1) +#define USBPD_REG_MASK_TIMER_TIMEOUT BIT(0) #define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p)+0x15) #define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p)+0x18) -#define USBPD_REG_MASK_SW_RESET_TX_STAT (1 << 3) -#define USBPD_REG_MASK_TX_BUSY_STAT (1 << 2) -#define USBPD_REG_MASK_TX_DISCARD_STAT (1 << 2) -#define USBPD_REG_MASK_TX_ERR_STAT (1 << 1) -#define USBPD_REG_MASK_TX_START (1 << 0) +#define USBPD_REG_MASK_SW_RESET_TX_STAT BIT(3) +#define USBPD_REG_MASK_TX_BUSY_STAT BIT(2) +#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(2) +#define USBPD_REG_MASK_TX_ERR_STAT BIT(1) +#define USBPD_REG_MASK_TX_START BIT(0) #define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x19) -#define USBPD_REG_MASK_CABLE_ENABLE (1 << 7) -#define USBPD_REG_MASK_SEND_HW_RESET (1 << 6) -#define USBPD_REG_MASK_SEND_BIST_MODE_2 (1 << 5) +#define USBPD_REG_MASK_CABLE_ENABLE BIT(7) +#define USBPD_REG_MASK_SEND_HW_RESET BIT(6) +#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(5) #define IT83XX_USBPD_MTSR1(p) REG8(IT83XX_USBPD_BASE(p)+0x1A) #define IT83XX_USBPD_VDMMCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1B) #define IT83XX_USBPD_MRSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1C) -#define USBPD_REG_MASK_RX_MSG_VALID (1 << 0) +#define USBPD_REG_MASK_RX_MSG_VALID BIT(0) #define IT83XX_USBPD_PEFSMR(p) REG8(IT83XX_USBPD_BASE(p)+0x1D) #define IT83XX_USBPD_PES0R(p) REG8(IT83XX_USBPD_BASE(p)+0x1E) #define IT83XX_USBPD_PES1R(p) REG8(IT83XX_USBPD_BASE(p)+0x1F) @@ -1252,11 +1252,11 @@ enum i2c_channels { #define IT83XX_USBPD_PDMHSR(p) REG8(IT83XX_USBPD_BASE(p)+0x65) #ifdef IT83XX_INTC_PLUG_IN_SUPPORT #define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p)+0x67) -#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT (1 << 7) -#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR (1 << 4) -#define USBPD_REG_PLUG_IN_OUT_SELECT (1 << 3) -#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE (1 << 1) -#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT (1 << 0) +#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7) +#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR BIT(4) +#define USBPD_REG_PLUG_IN_OUT_SELECT BIT(3) +#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1) +#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0) #endif //IT83XX_INTC_PLUG_IN_SUPPORT enum usbpd_port { @@ -1283,55 +1283,55 @@ enum usbpd_port { #define VW_VALID_FIELD(f) ((f) << 4) #define ESPI_SYSTEM_EVENT_VW_IDX_2 0x2 -#define VW_IDX_2_SLP_S3 (1 << 0) -#define VW_IDX_2_SLP_S4 (1 << 1) -#define VW_IDX_2_SLP_S5 (1 << 2) +#define VW_IDX_2_SLP_S3 BIT(0) +#define VW_IDX_2_SLP_S4 BIT(1) +#define VW_IDX_2_SLP_S5 BIT(2) #define ESPI_SYSTEM_EVENT_VW_IDX_3 0x3 -#define VW_IDX_3_SUS_STAT (1 << 0) -#define VW_IDX_3_PLTRST (1 << 1) -#define VW_IDX_3_OOB_RST_WARN (1 << 2) +#define VW_IDX_3_SUS_STAT BIT(0) +#define VW_IDX_3_PLTRST BIT(1) +#define VW_IDX_3_OOB_RST_WARN BIT(2) #define ESPI_SYSTEM_EVENT_VW_IDX_4 0x4 -#define VW_IDX_4_OOB_RST_ACK (1 << 0) -#define VW_IDX_4_WAKE (1 << 2) -#define VW_IDX_4_PME (1 << 3) +#define VW_IDX_4_OOB_RST_ACK BIT(0) +#define VW_IDX_4_WAKE BIT(2) +#define VW_IDX_4_PME BIT(3) #define ESPI_SYSTEM_EVENT_VW_IDX_5 0x5 -#define VW_IDX_5_SLAVE_BTLD_DONE (1 << 0) -#define VW_IDX_5_FATAL (1 << 1) -#define VW_IDX_5_NON_FATAL (1 << 2) -#define VW_IDX_5_SLAVE_BTLD_STATUS (1 << 3) +#define VW_IDX_5_SLAVE_BTLD_DONE BIT(0) +#define VW_IDX_5_FATAL BIT(1) +#define VW_IDX_5_NON_FATAL BIT(2) +#define VW_IDX_5_SLAVE_BTLD_STATUS BIT(3) #define VW_IDX_5_BTLD_STATUS_DONE (VW_IDX_5_SLAVE_BTLD_DONE | \ VW_IDX_5_SLAVE_BTLD_STATUS) #define ESPI_SYSTEM_EVENT_VW_IDX_6 0x6 -#define VW_IDX_6_SCI (1 << 0) -#define VW_IDX_6_SMI (1 << 1) -#define VW_IDX_6_RCIN (1 << 2) -#define VW_IDX_6_HOST_RST_ACK (1 << 3) +#define VW_IDX_6_SCI BIT(0) +#define VW_IDX_6_SMI BIT(1) +#define VW_IDX_6_RCIN BIT(2) +#define VW_IDX_6_HOST_RST_ACK BIT(3) #define ESPI_SYSTEM_EVENT_VW_IDX_7 0x7 -#define VW_IDX_7_HOST_RST_WARN (1 << 0) +#define VW_IDX_7_HOST_RST_WARN BIT(0) #define ESPI_SYSTEM_EVENT_VW_IDX_40 0x40 -#define VW_IDX_40_SUS_ACK (1 << 0) +#define VW_IDX_40_SUS_ACK BIT(0) #define ESPI_SYSTEM_EVENT_VW_IDX_41 0x41 -#define VW_IDX_41_SUS_WARN (1 << 0) -#define VW_IDX_41_SUS_PWRDN_ACK (1 << 1) -#define VW_IDX_41_SLP_A (1 << 3) +#define VW_IDX_41_SUS_WARN BIT(0) +#define VW_IDX_41_SUS_PWRDN_ACK BIT(1) +#define VW_IDX_41_SLP_A BIT(3) #define ESPI_SYSTEM_EVENT_VW_IDX_42 0x42 -#define VW_IDX_42_SLP_LAN (1 << 0) -#define VW_IDX_42_SLP_WLAN (1 << 1) +#define VW_IDX_42_SLP_LAN BIT(0) +#define VW_IDX_42_SLP_WLAN BIT(1) #define ESPI_SYSTEM_EVENT_VW_IDX_43 0x43 #define ESPI_SYSTEM_EVENT_VW_IDX_44 0x44 #define ESPI_SYSTEM_EVENT_VW_IDX_47 0x47 #define IT83XX_ESPI_VWCTRL0 REG8(IT83XX_ESPI_VW_BASE+0x90) -#define ESPI_INTERRUPT_EVENT_PUT_PC (1 << 7) +#define ESPI_INTERRUPT_EVENT_PUT_PC BIT(7) #define IT83XX_ESPI_VWCTRL1 REG8(IT83XX_ESPI_VW_BASE+0x91) #define IT83XX_ESPI_VWCTRL2 REG8(IT83XX_ESPI_VW_BASE+0x92) @@ -1348,7 +1348,7 @@ enum usbpd_port { #define IT83XX_USB_BASE 0x00F02F00 #define IT83XX_USB_P0MCR REG8(IT83XX_USB_BASE+0xE4) -#define USB_DP_DM_PULL_DOWN_EN (1 << 4) +#define USB_DP_DM_PULL_DOWN_EN BIT(4) /* Wake pin definitions, defined at board-level */ extern const enum gpio_signal hibernate_wake_pins[]; diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c index 98bf0e092a..d4f1987d4d 100644 --- a/chip/it83xx/system.c +++ b/chip/it83xx/system.c @@ -118,7 +118,7 @@ int system_is_reboot_warm(void) void chip_pre_init(void) { /* bit4, enable debug mode through SMBus */ - IT83XX_SMB_SLVISELR &= ~(1 << 4); + IT83XX_SMB_SLVISELR &= ~BIT(4); } #define BRAM_VALID_MAGIC 0x4252414D /* "BRAM" */ @@ -189,12 +189,12 @@ void system_reset(int flags) * If we are in debug mode, we need disable it before triggering * a soft reset or reset will fail. */ - IT83XX_SMB_SLVISELR |= (1 << 4); + IT83XX_SMB_SLVISELR |= BIT(4); /* bit0: enable watchdog hardware reset. */ #ifdef IT83XX_ETWD_HW_RESET_SUPPORT if (flags & SYSTEM_RESET_HARD) - IT83XX_GCTRL_ETWDUARTCR |= (1 << 0); + IT83XX_GCTRL_ETWDUARTCR |= BIT(0); #endif /* * Writing invalid key to watchdog module triggers a soft or hardware diff --git a/chip/it83xx/uart.c b/chip/it83xx/uart.c index 24dc2ec4c6..8cfbfdf466 100644 --- a/chip/it83xx/uart.c +++ b/chip/it83xx/uart.c @@ -209,10 +209,10 @@ void uart_init(void) * bit3: uart1 belongs to the EC side. * This is necessary for enabling eSPI module. */ - IT83XX_GCTRL_RSTDMMC |= (1 << 3); + IT83XX_GCTRL_RSTDMMC |= BIT(3); /* reset uart before config it */ - IT83XX_GCTRL_RSTC4 |= (1 << 1); + IT83XX_GCTRL_RSTC4 |= BIT(1); /* Waiting for when we can use the GPIO module to set pin muxing */ gpio_config_module(MODULE_UART, 1); @@ -229,9 +229,9 @@ void uart_init(void) #ifdef CONFIG_UART_HOST /* bit2, reset UART2 */ - IT83XX_GCTRL_RSTC4 |= (1 << 2); + IT83XX_GCTRL_RSTC4 |= BIT(2); /* SIN1/SOUT1 of UART 2 is enabled. */ - IT83XX_GPIO_GRC1 |= (1 << 2); + IT83XX_GPIO_GRC1 |= BIT(2); /* Config UART 2 */ host_uart_config(); #endif diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c index ee21170e34..c9641114ab 100644 --- a/chip/it83xx/watchdog.c +++ b/chip/it83xx/watchdog.c @@ -100,7 +100,7 @@ int watchdog_init(void) #ifdef CONFIG_HIBERNATE /* bit4: watchdog can be stopped. */ - IT83XX_ETWD_ETWCTRL |= (1 << 4); + IT83XX_ETWD_ETWCTRL |= BIT(4); #else /* Specify that watchdog cannot be stopped. */ IT83XX_ETWD_ETWCTRL = 0x00; diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c index 6f3efb700e..6a746fd9b5 100644 --- a/chip/lm4/i2c.c +++ b/chip/lm4/i2c.c @@ -21,22 +21,22 @@ #define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) /* Flags for writes to MCS */ -#define LM4_I2C_MCS_RUN (1 << 0) -#define LM4_I2C_MCS_START (1 << 1) -#define LM4_I2C_MCS_STOP (1 << 2) -#define LM4_I2C_MCS_ACK (1 << 3) -#define LM4_I2C_MCS_HS (1 << 4) -#define LM4_I2C_MCS_QCMD (1 << 5) +#define LM4_I2C_MCS_RUN BIT(0) +#define LM4_I2C_MCS_START BIT(1) +#define LM4_I2C_MCS_STOP BIT(2) +#define LM4_I2C_MCS_ACK BIT(3) +#define LM4_I2C_MCS_HS BIT(4) +#define LM4_I2C_MCS_QCMD BIT(5) /* Flags for reads from MCS */ -#define LM4_I2C_MCS_BUSY (1 << 0) -#define LM4_I2C_MCS_ERROR (1 << 1) -#define LM4_I2C_MCS_ADRACK (1 << 2) -#define LM4_I2C_MCS_DATACK (1 << 3) -#define LM4_I2C_MCS_ARBLST (1 << 4) -#define LM4_I2C_MCS_IDLE (1 << 5) -#define LM4_I2C_MCS_BUSBSY (1 << 6) -#define LM4_I2C_MCS_CLKTO (1 << 7) +#define LM4_I2C_MCS_BUSY BIT(0) +#define LM4_I2C_MCS_ERROR BIT(1) +#define LM4_I2C_MCS_ADRACK BIT(2) +#define LM4_I2C_MCS_DATACK BIT(3) +#define LM4_I2C_MCS_ARBLST BIT(4) +#define LM4_I2C_MCS_IDLE BIT(5) +#define LM4_I2C_MCS_BUSBSY BIT(6) +#define LM4_I2C_MCS_CLKTO BIT(7) /* * Minimum delay between resetting the port or sending a stop condition, and @@ -298,7 +298,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { - /* Conveniently, MBMON bit (1 << 1) is SDA and (1 << 0) is SCL. */ + /* Conveniently, MBMON bit BIT(1) is SDA and BIT(0) is SCL. */ return LM4_I2C_MBMON(port) & 0x03; } diff --git a/chip/lm4/keyboard_raw.c b/chip/lm4/keyboard_raw.c index 66d66de1fa..85042ce85e 100644 --- a/chip/lm4/keyboard_raw.c +++ b/chip/lm4/keyboard_raw.c @@ -34,7 +34,7 @@ void keyboard_raw_init(void) * When column 2 is inverted, the Silego has a pulldown instead of a * pullup. So drive it push-pull instead of open-drain. */ - LM4_GPIO_ODR(LM4_GPIO_P) &= ~(1 << 2); + LM4_GPIO_ODR(LM4_GPIO_P) &= ~BIT(2); #endif /* Set row inputs with pull-up */ @@ -72,7 +72,7 @@ test_mockable void keyboard_raw_drive_column(int col) #ifdef CONFIG_KEYBOARD_COL2_INVERTED /* Invert column 2 output */ - mask ^= (1 << 2); + mask ^= BIT(2); #endif LM4_GPIO_DATA(LM4_GPIO_P, 0xff) = mask & 0xff; diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c index f2f1cb0549..745e5e5465 100644 --- a/chip/lm4/lpc.c +++ b/chip/lm4/lpc.c @@ -405,7 +405,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask) int lpc_get_pltrst_asserted(void) { - return (LM4_LPC_LPCSTS & (1<<10)) ? 1 : 0; + return (LM4_LPC_LPCSTS & BIT(10)) ? 1 : 0; } /** @@ -594,8 +594,8 @@ void lpc_interrupt(void) #endif /* Debugging: print changes to LPC0RESET */ - if (mis & (1 << 31)) { - if (LM4_LPC_LPCSTS & (1 << 10)) { + if (mis & BIT(31)) { + if (LM4_LPC_LPCSTS & BIT(10)) { int i; /* Store port 80 reset event */ @@ -682,7 +682,7 @@ static void lpc_init(void) * data writes, pool bytes 0(data)/1(cmd) */ LM4_LPC_ADR(LPC_CH_KEYBOARD) = 0x60; - LM4_LPC_CTL(LPC_CH_KEYBOARD) = (1 << 24/* IRQSEL1 */) | + LM4_LPC_CTL(LPC_CH_KEYBOARD) = (BIT(24)/* IRQSEL1 */) | (0 << 18/* IRQEN1 */) | (LPC_POOL_OFFS_KEYBOARD << (5 - 1)); LM4_LPC_ST(LPC_CH_KEYBOARD) = 0; /* Unmask interrupt for host command/data writes and data reads */ @@ -743,7 +743,7 @@ static void lpc_init(void) * Unmask LPC bus reset interrupt. This lets us monitor the PCH * PLTRST# signal for debugging. */ - LM4_LPC_LPCIM |= (1 << 31); + LM4_LPC_LPCIM |= BIT(31); /* Enable LPC channels */ LM4_LPC_LPCCTL = LM4_LPC_SCI_CLK_1 | @@ -820,7 +820,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 2) | (1 << 3); + r->protocol_versions = BIT(2) | BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h index 15c91d1ca3..7fad67c181 100644 --- a/chip/lm4/registers.h +++ b/chip/lm4/registers.h @@ -41,11 +41,11 @@ static inline int lm4_spi_addr(int ch, int offset) #define LM4_SSI_CR1(ch) LM4SSIREG(ch, 0x004) #define LM4_SSI_DR(ch) LM4SSIREG(ch, 0x008) #define LM4_SSI_SR(ch) LM4SSIREG(ch, 0x00c) -#define LM4_SSI_SR_TFE (1 << 0) /* Transmit FIFO empty */ -#define LM4_SSI_SR_TNF (1 << 1) /* Transmit FIFO not full */ -#define LM4_SSI_SR_RNE (1 << 2) /* Receive FIFO not empty */ -#define LM4_SSI_SR_RFF (1 << 3) /* Receive FIFO full */ -#define LM4_SSI_SR_BSY (1 << 4) /* Busy */ +#define LM4_SSI_SR_TFE BIT(0) /* Transmit FIFO empty */ +#define LM4_SSI_SR_TNF BIT(1) /* Transmit FIFO not full */ +#define LM4_SSI_SR_RNE BIT(2) /* Receive FIFO not empty */ +#define LM4_SSI_SR_RFF BIT(3) /* Receive FIFO full */ +#define LM4_SSI_SR_BSY BIT(4) /* Busy */ #define LM4_SSI_CPSR(ch) LM4SSIREG(ch, 0x010) #define LM4_SSI_IM(ch) LM4SSIREG(ch, 0x014) #define LM4_SSI_RIS(ch) LM4SSIREG(ch, 0x018) @@ -85,7 +85,7 @@ static inline int lm4_adc_addr(int ss, int offset) #define LM4_ADC_SSEMUX(ss) LM4ADCREG(ss, 0x018) #define LM4_LPC_LPCCTL REG32(0x40080000) -#define LM4_LPC_SCI_START (1 << 9) /* Start a pulse on LPC0SCI signal */ +#define LM4_LPC_SCI_START BIT(9) /* Start a pulse on LPC0SCI signal */ #define LM4_LPC_SCI_CLK_1 (0 << 10) /* SCI asserted for 1 clock period */ #define LM4_LPC_SCI_CLK_2 (1 << 10) /* SCI asserted for 2 clock periods */ #define LM4_LPC_SCI_CLK_4 (2 << 10) /* SCI asserted for 4 clock periods */ @@ -115,13 +115,13 @@ static inline int lm4_lpc_addr(int ch, int offset) #define LM4LPCREG(ch, offset) REG32(lm4_lpc_addr(ch, offset)) #define LM4_LPC_CTL(ch) LM4LPCREG(ch, 0x000) #define LM4_LPC_ST(ch) LM4LPCREG(ch, 0x004) -#define LM4_LPC_ST_TOH (1 << 0) /* TO Host bit */ -#define LM4_LPC_ST_FRMH (1 << 1) /* FRoM Host bit */ -#define LM4_LPC_ST_CMD (1 << 3) /* Last from-host byte was command */ -#define LM4_LPC_ST_BURST (1 << 8) -#define LM4_LPC_ST_SCI (1 << 9) -#define LM4_LPC_ST_SMI (1 << 10) -#define LM4_LPC_ST_BUSY (1 << 12) +#define LM4_LPC_ST_TOH BIT(0) /* TO Host bit */ +#define LM4_LPC_ST_FRMH BIT(1) /* FRoM Host bit */ +#define LM4_LPC_ST_CMD BIT(3) /* Last from-host byte was command */ +#define LM4_LPC_ST_BURST BIT(8) +#define LM4_LPC_ST_SCI BIT(9) +#define LM4_LPC_ST_SMI BIT(10) +#define LM4_LPC_ST_BUSY BIT(12) #define LM4_LPC_ADR(ch) LM4LPCREG(ch, 0x008) #define LM4_LPC_POOL_BYTES 1024 /* Size of LPCPOOL in bytes */ #define LM4_LPC_LPCPOOL ((volatile unsigned char *)0x40080400) @@ -186,12 +186,12 @@ static inline int lm4_fan_addr(int ch, int offset) #define LM4_HIBERNATE_HIBRTCM0 REG32(0x400fc004) #define LM4_HIBERNATE_HIBRTCLD REG32(0x400fc00c) #define LM4_HIBERNATE_HIBCTL REG32(0x400fc010) -#define LM4_HIBCTL_WRC (1 << 31) -#define LM4_HIBCTL_CLK32EN (1 << 6) -#define LM4_HIBCTL_PINWEN (1 << 4) -#define LM4_HIBCTL_RTCWEN (1 << 3) -#define LM4_HIBCTL_HIBREQ (1 << 1) -#define LM4_HIBCTL_RTCEN (1 << 0) +#define LM4_HIBCTL_WRC BIT(31) +#define LM4_HIBCTL_CLK32EN BIT(6) +#define LM4_HIBCTL_PINWEN BIT(4) +#define LM4_HIBCTL_RTCWEN BIT(3) +#define LM4_HIBCTL_HIBREQ BIT(1) +#define LM4_HIBCTL_RTCEN BIT(0) #define LM4_HIBERNATE_HIBIM REG32(0x400fc014) #define LM4_HIBERNATE_HIBRIS REG32(0x400fc018) #define LM4_HIBERNATE_HIBMIS REG32(0x400fc01c) @@ -228,22 +228,22 @@ static inline int lm4_fan_addr(int ch, int offset) #define LM4_SYSTEM_MISC REG32(0x400fe058) #define LM4_SYSTEM_RESC REG32(0x400fe05c) #define LM4_SYSTEM_RCC REG32(0x400fe060) -#define LM4_SYSTEM_RCC_ACG (1 << 27) +#define LM4_SYSTEM_RCC_ACG BIT(27) #define LM4_SYSTEM_RCC_SYSDIV(x) (((x) & 0xf) << 23) -#define LM4_SYSTEM_RCC_USESYSDIV (1 << 22) -#define LM4_SYSTEM_RCC_PWRDN (1 << 13) -#define LM4_SYSTEM_RCC_BYPASS (1 << 11) +#define LM4_SYSTEM_RCC_USESYSDIV BIT(22) +#define LM4_SYSTEM_RCC_PWRDN BIT(13) +#define LM4_SYSTEM_RCC_BYPASS BIT(11) #define LM4_SYSTEM_RCC_XTAL(x) (((x) & 0x1f) << 6) #define LM4_SYSTEM_RCC_OSCSRC(x) (((x) & 0x3) << 4) -#define LM4_SYSTEM_RCC_IOSCDIS (1 << 1) -#define LM4_SYSTEM_RCC_MOSCDIS (1 << 0) +#define LM4_SYSTEM_RCC_IOSCDIS BIT(1) +#define LM4_SYSTEM_RCC_MOSCDIS BIT(0) #define LM4_SYSTEM_RCC2 REG32(0x400fe070) -#define LM4_SYSTEM_RCC2_USERCC2 (1 << 31) -#define LM4_SYSTEM_RCC2_DIV400 (1 << 30) +#define LM4_SYSTEM_RCC2_USERCC2 BIT(31) +#define LM4_SYSTEM_RCC2_DIV400 BIT(30) #define LM4_SYSTEM_RCC2_SYSDIV2(x) (((x) & 0x3f) << 23) -#define LM4_SYSTEM_RCC2_SYSDIV2LSB (1 << 22) -#define LM4_SYSTEM_RCC2_PWRDN2 (1 << 13) -#define LM4_SYSTEM_RCC2_BYPASS2 (1 << 11) +#define LM4_SYSTEM_RCC2_SYSDIV2LSB BIT(22) +#define LM4_SYSTEM_RCC2_PWRDN2 BIT(13) +#define LM4_SYSTEM_RCC2_BYPASS2 BIT(11) #define LM4_SYSTEM_RCC2_OSCSRC2(x) (((x) & 0x7) << 4) #define LM4_SYSTEM_MOSCCTL REG32(0x400fe07c) #define LM4_SYSTEM_DSLPCLKCFG REG32(0x400fe144) diff --git a/chip/lm4/system.c b/chip/lm4/system.c index 45f6b91809..ce3d353bed 100644 --- a/chip/lm4/system.c +++ b/chip/lm4/system.c @@ -30,9 +30,9 @@ enum hibdata_index { }; /* Flags for HIBDATA_INDEX_WAKE */ -#define HIBDATA_WAKE_RTC (1 << 0) /* RTC alarm */ -#define HIBDATA_WAKE_HARD_RESET (1 << 1) /* Hard reset via short RTC alarm */ -#define HIBDATA_WAKE_PIN (1 << 2) /* Wake pin */ +#define HIBDATA_WAKE_RTC BIT(0) /* RTC alarm */ +#define HIBDATA_WAKE_HARD_RESET BIT(1) /* Hard reset via short RTC alarm */ +#define HIBDATA_WAKE_PIN BIT(2) /* Wake pin */ /* * Time to hibernate to trigger a power-on reset. 50 ms is sufficient for the diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c index 583ace0582..e7ff5e2e83 100644 --- a/chip/lm4/watchdog.c +++ b/chip/lm4/watchdog.c @@ -101,7 +101,7 @@ int watchdog_init(void) LM4_WATCHDOG_LOCK(0) = LM4_WATCHDOG_MAGIC_WORD; /* De-activate the watchdog when the JTAG stops the CPU */ - LM4_WATCHDOG_TEST(0) |= 1 << 8; + LM4_WATCHDOG_TEST(0) |= BIT(8); /* Reset after 2 time-out, activate the watchdog and lock the control * register. */ diff --git a/chip/mchp/adc.c b/chip/mchp/adc.c index 6278bc1ebd..e8ec10a0e5 100644 --- a/chip/mchp/adc.c +++ b/chip/mchp/adc.c @@ -50,14 +50,14 @@ static int start_single_and_wait(int timeout) /* clear all R/W1C channel status */ MCHP_ADC_STS = 0xffffu; /* clear R/W1C single done status */ - MCHP_ADC_CTRL |= (1 << 7); + MCHP_ADC_CTRL |= BIT(7); /* clear GIRQ single status */ MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; /* make sure all writes are issued before starting conversion */ asm volatile ("dsb"); /* Start conversion */ - MCHP_ADC_CTRL |= 1 << 1; + MCHP_ADC_CTRL |= BIT(1); MCHP_INT_ENABLE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; @@ -131,7 +131,7 @@ static void adc_init(void) MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_ADC); /* Activate ADC module */ - MCHP_ADC_CTRL |= 1 << 0; + MCHP_ADC_CTRL |= BIT(0); /* Enable interrupt */ task_waiting = TASK_ID_INVALID; @@ -148,7 +148,7 @@ void adc_interrupt(void) MCHP_ADC_STS = 0xffffu; /* Clear interrupt status bit */ - MCHP_ADC_CTRL |= 1 << 7; + MCHP_ADC_CTRL |= BIT(7); MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c index 59731830cf..6046eee7fb 100644 --- a/chip/mchp/clock.c +++ b/chip/mchp/clock.c @@ -341,7 +341,7 @@ static void prepare_for_deep_sleep(void) /* Enable assertion of DeepSleep signals * from the core when core enters sleep. */ - CPU_SCB_SYSCTRL |= (1 << 2); + CPU_SCB_SYSCTRL |= BIT(2); /* Stop timers */ MCHP_TMR32_CTL(0) &= ~1; @@ -422,7 +422,7 @@ static void resume_from_deep_sleep(void) MCHP_PCR_SYS_SLP_CTL = 0x00; /* default */ /* Disable assertion of DeepSleep signal when core executes WFI */ - CPU_SCB_SYSCTRL &= ~(1 << 2); + CPU_SCB_SYSCTRL &= ~BIT(2); #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG print_saved_regs(); @@ -483,7 +483,7 @@ static void resume_from_deep_sleep(void) #ifdef CONFIG_WATCHDOG #ifdef CONFIG_CHIPSET_DEBUG /* enable WDG stall on active JTAG and do not start */ - MCHP_WDG_CTL = (1 << 4); + MCHP_WDG_CTL = BIT(4); #else MCHP_WDG_CTL |= 1; #endif diff --git a/chip/mchp/fan.c b/chip/mchp/fan.c index 6f89f06673..dc939bb58f 100644 --- a/chip/mchp/fan.c +++ b/chip/mchp/fan.c @@ -82,15 +82,15 @@ int fan_get_duty(int ch) int fan_get_rpm_mode(int ch) { - return !!(MCHP_FAN_CFG1(0) & (1 << 7)); + return !!(MCHP_FAN_CFG1(0) & BIT(7)); } void fan_set_rpm_mode(int ch, int rpm_mode) { if (rpm_mode) - MCHP_FAN_CFG1(0) |= 1 << 7; + MCHP_FAN_CFG1(0) |= BIT(7); else - MCHP_FAN_CFG1(0) &= ~(1 << 7); + MCHP_FAN_CFG1(0) &= ~BIT(7); clear_status(); } @@ -118,7 +118,7 @@ enum fan_status fan_get_status(int ch) { uint8_t sts = MCHP_FAN_STATUS(0); - if (sts & ((1 << 5) | (1 << 1))) + if (sts & (BIT(5) | BIT(1))) return FAN_STATUS_FRUSTRATED; if (fan_get_rpm_actual(ch) == 0) return FAN_STATUS_STOPPED; diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c index 282c643a95..aa95b8fb0d 100644 --- a/chip/mchp/gpio.c +++ b/chip/mchp/gpio.c @@ -57,7 +57,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) while (mask) { i = __builtin_ffs(mask) - 1; val = MCHP_GPIO_CTL(port, i); - val &= ~((1 << 12) | (1 << 13)); + val &= ~(BIT(12) | BIT(13)); /* mux_control = 0 indicates GPIO */ if (func > 0) val |= (func & 0x3) << 12; @@ -77,7 +77,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal) i = GPIO_MASK_TO_NUM(mask); val = MCHP_GPIO_CTL(gpio_list[signal].port, i); - return (val & (1 << 24)) ? 1 : 0; + return (val & BIT(24)) ? 1 : 0; } void gpio_set_level(enum gpio_signal signal, int value) @@ -90,9 +90,9 @@ void gpio_set_level(enum gpio_signal signal, int value) i = GPIO_MASK_TO_NUM(mask); if (value) - MCHP_GPIO_CTL(gpio_list[signal].port, i) |= (1 << 16); + MCHP_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16); else - MCHP_GPIO_CTL(gpio_list[signal].port, i) &= ~(1 << 16); + MCHP_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16); } /* diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c index 1cb2b4fbcb..f8b556d389 100644 --- a/chip/mchp/gpspi.c +++ b/chip/mchp/gpspi.c @@ -109,7 +109,7 @@ int gpspi_transaction_async(const struct spi_device_t *spi_device, ctrl = gpspi_port_to_ctrl_id(hw_port); /* Disable auto read */ - MCHP_SPI_CR(ctrl) &= ~(1 << 5); + MCHP_SPI_CR(ctrl) &= ~BIT(5); if ((txdata != NULL) && (txdata != 0)) { #ifdef CONFIG_MCHP_GPSPI_TX_DMA @@ -151,7 +151,7 @@ int gpspi_transaction_async(const struct spi_device_t *spi_device, if (!cs_asserted) gpio_set_level(spi_device->gpio_cs, 0); /* Enable auto read */ - MCHP_SPI_CR(ctrl) |= 1 << 5; + MCHP_SPI_CR(ctrl) |= BIT(5); dma_start_rx(opdma, rxlen, rxdata); MCHP_SPI_TD(ctrl) = 0; ret = EC_SUCCESS; @@ -180,7 +180,7 @@ int gpspi_transaction_flush(const struct spi_device_t *spi_device) ret = dma_wait(chan); /* Disable auto read */ - MCHP_SPI_CR(ctrl) &= ~(1 << 5); + MCHP_SPI_CR(ctrl) &= ~BIT(5); deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; /* Wait for FIFO empty SPISR_TXBE */ diff --git a/chip/mchp/hwtimer.c b/chip/mchp/hwtimer.c index fa68d09f18..a69fa4ab7e 100644 --- a/chip/mchp/hwtimer.c +++ b/chip/mchp/hwtimer.c @@ -18,7 +18,7 @@ void __hw_clock_event_set(uint32_t deadline) { MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) - (0xffffffff - deadline); - MCHP_TMR32_CTL(1) |= (1 << 5); + MCHP_TMR32_CTL(1) |= BIT(5); } uint32_t __hw_clock_event_get(void) @@ -28,7 +28,7 @@ uint32_t __hw_clock_event_get(void) void __hw_clock_event_clear(void) { - MCHP_TMR32_CTL(1) &= ~(1 << 5); + MCHP_TMR32_CTL(1) &= ~BIT(5); } uint32_t __hw_clock_source_read(void) @@ -38,9 +38,9 @@ uint32_t __hw_clock_source_read(void) void __hw_clock_source_set(uint32_t ts) { - MCHP_TMR32_CTL(0) &= ~(1 << 5); + MCHP_TMR32_CTL(0) &= ~BIT(5); MCHP_TMR32_CNT(0) = 0xffffffff - ts; - MCHP_TMR32_CTL(0) |= (1 << 5); + MCHP_TMR32_CTL(0) |= BIT(5); } /* @@ -66,10 +66,10 @@ static void configure_timer(int timer_id) uint32_t val; /* Ensure timer is not running */ - MCHP_TMR32_CTL(timer_id) &= ~(1 << 5); + MCHP_TMR32_CTL(timer_id) &= ~BIT(5); /* Enable timer */ - MCHP_TMR32_CTL(timer_id) |= (1 << 0); + MCHP_TMR32_CTL(timer_id) |= BIT(0); val = MCHP_TMR32_CTL(timer_id); @@ -103,10 +103,10 @@ int __hw_clock_source_init(uint32_t start_t) MCHP_TMR32_CNT(0) = 0xffffffff - start_t; /* Auto restart */ - MCHP_TMR32_CTL(0) |= (1 << 3); + MCHP_TMR32_CTL(0) |= BIT(3); /* Start counting in timer 0 */ - MCHP_TMR32_CTL(0) |= (1 << 5); + MCHP_TMR32_CTL(0) |= BIT(5); /* Enable interrupt */ task_enable_irq(MCHP_IRQ_TIMER32_0); diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c index bfe4890d4f..f47f209947 100644 --- a/chip/mchp/i2c.c +++ b/chip/mchp/i2c.c @@ -46,44 +46,44 @@ #define SPEED_100KHZ_IDLE_SCALING 0x01FC01EDul #define SPEED_100KHZ_TIMEOUT_SCALING 0x4B9CC2C7ul /* Status */ -#define STS_NBB (1 << 0) /* Bus busy */ -#define STS_LAB (1 << 1) /* Arbitration lost */ -#define STS_LRB (1 << 3) /* Last received bit */ -#define STS_BER (1 << 4) /* Bus error */ -#define STS_PIN (1 << 7) /* Pending interrupt */ +#define STS_NBB BIT(0) /* Bus busy */ +#define STS_LAB BIT(1) /* Arbitration lost */ +#define STS_LRB BIT(3) /* Last received bit */ +#define STS_BER BIT(4) /* Bus error */ +#define STS_PIN BIT(7) /* Pending interrupt */ /* Control */ -#define CTRL_ACK (1 << 0) /* Acknowledge */ -#define CTRL_STO (1 << 1) /* STOP */ -#define CTRL_STA (1 << 2) /* START */ -#define CTRL_ENI (1 << 3) /* Enable interrupt */ -#define CTRL_ESO (1 << 6) /* Enable serial output */ -#define CTRL_PIN (1 << 7) /* Pending interrupt not */ +#define CTRL_ACK BIT(0) /* Acknowledge */ +#define CTRL_STO BIT(1) /* STOP */ +#define CTRL_STA BIT(2) /* START */ +#define CTRL_ENI BIT(3) /* Enable interrupt */ +#define CTRL_ESO BIT(6) /* Enable serial output */ +#define CTRL_PIN BIT(7) /* Pending interrupt not */ /* Completion */ -#define COMP_DTEN (1 << 2) /* enable device timeouts */ -#define COMP_MCEN (1 << 3) /* enable master cumulative timeouts */ -#define COMP_SCEN (1 << 4) /* enable slave cumulative timeouts */ -#define COMP_BIDEN (1 << 5) /* enable Bus idle timeouts */ -#define COMP_IDLE (1 << 29) /* i2c bus is idle */ +#define COMP_DTEN BIT(2) /* enable device timeouts */ +#define COMP_MCEN BIT(3) /* enable master cumulative timeouts */ +#define COMP_SCEN BIT(4) /* enable slave cumulative timeouts */ +#define COMP_BIDEN BIT(5) /* enable Bus idle timeouts */ +#define COMP_IDLE BIT(29) /* i2c bus is idle */ #define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ /* Configuration */ #define CFG_PORT_MASK (0x0F) /* port selection field */ -#define CFG_TCEN (1 << 4) /* Enable HW bus timeouts */ -#define CFG_FEN (1 << 8) /* enable input filtering */ -#define CFG_RESET (1 << 9) /* reset controller */ -#define CFG_ENABLE (1 << 10) /* enable controller */ -#define CFG_GC_DIS (1 << 14) /* disable general call address */ -#define CFG_ENIDI (1 << 29) /* Enable I2C idle interrupt */ +#define CFG_TCEN BIT(4) /* Enable HW bus timeouts */ +#define CFG_FEN BIT(8) /* enable input filtering */ +#define CFG_RESET BIT(9) /* reset controller */ +#define CFG_ENABLE BIT(10) /* enable controller */ +#define CFG_GC_DIS BIT(14) /* disable general call address */ +#define CFG_ENIDI BIT(29) /* Enable I2C idle interrupt */ /* Enable network layer master done interrupt */ -#define CFG_ENMI (1 << 30) +#define CFG_ENMI BIT(30) /* Enable network layer slave done interrupt */ -#define CFG_ENSI (1 << 31) +#define CFG_ENSI BIT(31) /* Master Command */ -#define MCMD_MRUN (1 << 0) -#define MCMD_MPROCEED (1 << 1) -#define MCMD_START0 (1 << 8) -#define MCMD_STARTN (1 << 9) -#define MCMD_STOP (1 << 10) -#define MCMD_READM (1 << 12) +#define MCMD_MRUN BIT(0) +#define MCMD_MPROCEED BIT(1) +#define MCMD_START0 BIT(8) +#define MCMD_STARTN BIT(9) +#define MCMD_STOP BIT(10) +#define MCMD_READM BIT(12) #define MCMD_WCNT_BITPOS (16) #define MCMD_WCNT_MASK0 (0xFF) #define MCMD_WCNT_MASK (0xFF << 16) @@ -342,9 +342,9 @@ static void reset_controller(int controller) int i; /* Reset asserted for at least one AHB clock */ - MCHP_I2C_CONFIG(controller) |= 1 << 9; + MCHP_I2C_CONFIG(controller) |= BIT(9); MCHP_EC_ID_RO = 0; - MCHP_I2C_CONFIG(controller) &= ~(1 << 9); + MCHP_I2C_CONFIG(controller) &= ~BIT(9); for (i = 0; i < i2c_ports_used; ++i) if (controller == i2c_port_to_controller(i2c_ports[i].port)) { @@ -464,9 +464,9 @@ static void select_port(int port, int controller) if ((MCHP_I2C_CONFIG(controller) & 0x0f) == port_sel) return; - MCHP_I2C_CONFIG(controller) |= 1 << 9; + MCHP_I2C_CONFIG(controller) |= BIT(9); MCHP_EC_ID_RO = 0; /* dummy write to read-only as delay */ - MCHP_I2C_CONFIG(controller) &= ~(1 << 9); + MCHP_I2C_CONFIG(controller) &= ~BIT(9); configure_controller(controller, port_sel, i2c_ports[port].kbps); } diff --git a/chip/mchp/keyboard_raw.c b/chip/mchp/keyboard_raw.c index ef968c0eb8..946ea1ca90 100644 --- a/chip/mchp/keyboard_raw.c +++ b/chip/mchp/keyboard_raw.c @@ -39,19 +39,19 @@ void keyboard_raw_task_start(void) test_mockable void keyboard_raw_drive_column(int out) { if (out == KEYBOARD_COLUMN_ALL) { - MCHP_KS_KSO_SEL = 1 << 5; /* KSEN=0, KSALL=1 */ + MCHP_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 1); #endif } else if (out == KEYBOARD_COLUMN_NONE) { - MCHP_KS_KSO_SEL = 1 << 6; /* KSEN=1 */ + MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 0); #endif } else { #ifdef CONFIG_KEYBOARD_COL2_INVERTED if (out == 2) { - MCHP_KS_KSO_SEL = 1 << 6; /* KSEN=1 */ + MCHP_KS_KSO_SEL = BIT(6); /* KSEN=1 */ gpio_set_level(GPIO_KBD_KSO2, 1); } else { MCHP_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; @@ -100,5 +100,5 @@ DECLARE_IRQ(MCHP_IRQ_KSC_INT, keyboard_raw_interrupt, 1); int keyboard_raw_is_input_low(int port, int id) { - return (MCHP_GPIO_CTL(port, id) & (1 << 24)) == 0; + return (MCHP_GPIO_CTL(port, id) & BIT(24)) == 0; } diff --git a/chip/mchp/lfw/ec_lfw.c b/chip/mchp/lfw/ec_lfw.c index a9f923d5bb..111e753d3b 100644 --- a/chip/mchp/lfw/ec_lfw.c +++ b/chip/mchp/lfw/ec_lfw.c @@ -100,10 +100,10 @@ void timer_init(void) uint32_t val = 0; /* Ensure timer is not running */ - MCHP_TMR32_CTL(0) &= ~(1 << 5); + MCHP_TMR32_CTL(0) &= ~BIT(5); /* Enable timer */ - MCHP_TMR32_CTL(0) |= (1 << 0); + MCHP_TMR32_CTL(0) |= BIT(0); val = MCHP_TMR32_CTL(0); @@ -119,10 +119,10 @@ void timer_init(void) MCHP_TMR32_CNT(0) = 0xffffffff; /* Auto restart */ - MCHP_TMR32_CTL(0) |= (1 << 3); + MCHP_TMR32_CTL(0) |= BIT(3); /* Start counting in timer 0 */ - MCHP_TMR32_CTL(0) |= (1 << 5); + MCHP_TMR32_CTL(0) |= BIT(5); } @@ -246,7 +246,7 @@ void uart_write_c(char c) uart_write_c('\r'); /* Wait for space in transmit FIFO. */ - while (!(MCHP_UART_LSR(0) & (1 << 5))) + while (!(MCHP_UART_LSR(0) & BIT(5))) ; MCHP_UART_TB(0) = c; } @@ -282,31 +282,31 @@ void jump_to_image(uintptr_t init_addr) void uart_init(void) { /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MCHP_UART_CFG(0) &= ~(1 << 1); + MCHP_UART_CFG(0) &= ~BIT(1); /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ /* Set CLK_SRC = 0 */ - MCHP_UART_CFG(0) &= ~(1 << 0); + MCHP_UART_CFG(0) &= ~BIT(0); /* Set DLAB = 1 */ - MCHP_UART_LCR(0) |= (1 << 7); + MCHP_UART_LCR(0) |= BIT(7); /* PBRG0/PBRG1 */ MCHP_UART_PBRG0(0) = 1; MCHP_UART_PBRG1(0) = 0; /* Set DLAB = 0 */ - MCHP_UART_LCR(0) &= ~(1 << 7); + MCHP_UART_LCR(0) &= ~BIT(7); /* Set word length to 8-bit */ - MCHP_UART_LCR(0) |= (1 << 0) | (1 << 1); + MCHP_UART_LCR(0) |= BIT(0) | BIT(1); /* Enable FIFO */ - MCHP_UART_FCR(0) = (1 << 0); + MCHP_UART_FCR(0) = BIT(0); /* Activate UART */ - MCHP_UART_ACT(0) |= (1 << 0); + MCHP_UART_ACT(0) |= BIT(0); gpio_config_module(MODULE_UART, 1); } diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c index 96d68898c2..32e1c81c95 100644 --- a/chip/mchp/lpc.c +++ b/chip/mchp/lpc.c @@ -348,7 +348,7 @@ void chip_8042_config(uint32_t io_base) MCHP_LPC_8042_BAR = (io_base << 16) + (1ul << 15); #endif /* Set up indication of Auxiliary sts */ - MCHP_8042_KB_CTRL |= 1 << 7; + MCHP_8042_KB_CTRL |= BIT(7); MCHP_8042_ACT |= 1; @@ -360,7 +360,7 @@ void chip_8042_config(uint32_t io_base) #ifndef CONFIG_KEYBOARD_IRQ_GPIO /* Set up SERIRQ for keyboard */ - MCHP_8042_KB_CTRL |= (1 << 5); + MCHP_8042_KB_CTRL |= BIT(5); MCHP_LPC_SIRQ(1) = 0x01; #endif } @@ -464,7 +464,7 @@ static void setup_lpc(void) #ifndef CONFIG_KEYBOARD_IRQ_GPIO /* Set up SERIRQ for keyboard */ - MCHP_8042_KB_CTRL |= (1 << 5); + MCHP_8042_KB_CTRL |= BIT(5); MCHP_LPC_SIRQ(1) = 0x01; #endif /* EMI0 at IO 0x800 */ @@ -815,7 +815,7 @@ void kb_ibf_interrupt(void) { if (lpc_keyboard_input_pending()) keyboard_host_write(MCHP_8042_H2E, - MCHP_8042_STS & (1 << 3)); + MCHP_8042_STS & BIT(3)); MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_IBF_GIRQ_BIT; task_wake(TASK_ID_KEYPROTO); @@ -844,12 +844,12 @@ DECLARE_IRQ(MCHP_IRQ_8042EM_OBE, kb_obe_interrupt, 1); */ int lpc_keyboard_has_char(void) { - return (MCHP_8042_STS & (1 << 0)) ? 1 : 0; + return (MCHP_8042_STS & BIT(0)) ? 1 : 0; } int lpc_keyboard_input_pending(void) { - return (MCHP_8042_STS & (1 << 1)) ? 1 : 0; + return (MCHP_8042_STS & BIT(1)) ? 1 : 0; } /* @@ -944,7 +944,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) CPUTS("MEC1701 Handler EC_CMD_GET_PROTOCOL_INFO"); memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/mchp/pwm.c b/chip/mchp/pwm.c index 54200c7890..53a8c15806 100644 --- a/chip/mchp/pwm.c +++ b/chip/mchp/pwm.c @@ -110,8 +110,8 @@ static void pwm_configure(int ch, int active_low, int clock_low) * clock_low=1 selects the 100kHz_Clk source */ MCHP_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ - (active_low ? (1 << 2) : 0) | - (clock_low ? (1 << 1) : 0); + (active_low ? BIT(2) : 0) | + (clock_low ? BIT(1) : 0); } static const uint16_t pwm_pcr[MCHP_PWM_ID_MAX] = { diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h index 2fcbd9ab46..f7ef36e68c 100644 --- a/chip/mchp/registers.h +++ b/chip/mchp/registers.h @@ -90,64 +90,64 @@ #define MCHP_PCR_JTAG (0x0000) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN0_ISPI (1 << 2) -#define MCHP_PCR_SLP_EN0_EFUSE (1 << 1) -#define MCHP_PCR_SLP_EN0_JTAG (1 << 0) +#define MCHP_PCR_SLP_EN0_ISPI BIT(2) +#define MCHP_PCR_SLP_EN0_EFUSE BIT(1) +#define MCHP_PCR_SLP_EN0_JTAG BIT(0) #define MCHP_PCR_SLP_EN0_SLEEP 0x07ul /* Sleep Enable, Clock Required, Reset on Sleep 1 bits */ -#define MCHP_PCR_BTMR16_1 ((1 << 8) + 31) -#define MCHP_PCR_BTMR16_0 ((1 << 8) + 30) -#define MCHP_PCR_ECS ((1 << 8) + 29) -#define MCHP_PCR_PWM8 ((1 << 8) + 27) -#define MCHP_PCR_PWM7 ((1 << 8) + 26) -#define MCHP_PCR_PWM6 ((1 << 8) + 25) -#define MCHP_PCR_PWM5 ((1 << 8) + 24) -#define MCHP_PCR_PWM4 ((1 << 8) + 23) -#define MCHP_PCR_PWM3 ((1 << 8) + 22) -#define MCHP_PCR_PWM2 ((1 << 8) + 21) -#define MCHP_PCR_PWM1 ((1 << 8) + 20) -#define MCHP_PCR_TACH2 ((1 << 8) + 12) -#define MCHP_PCR_TACH1 ((1 << 8) + 11) -#define MCHP_PCR_I2C0 ((1 << 8) + 10) -#define MCHP_PCR_WDT ((1 << 8) + 9) -#define MCHP_PCR_CPU ((1 << 8) + 8) -#define MCHP_PCR_TFDP ((1 << 8) + 7) -#define MCHP_PCR_DMA ((1 << 8) + 6) -#define MCHP_PCR_PMC ((1 << 8) + 5) -#define MCHP_PCR_PWM0 ((1 << 8) + 4) -#define MCHP_PCR_TACH0 ((1 << 8) + 2) -#define MCHP_PCR_PECI ((1 << 8) + 1) -#define MCHP_PCR_ECIA ((1 << 8) + 0) +#define MCHP_PCR_BTMR16_1 (BIT(8) + 31) +#define MCHP_PCR_BTMR16_0 (BIT(8) + 30) +#define MCHP_PCR_ECS (BIT(8) + 29) +#define MCHP_PCR_PWM8 (BIT(8) + 27) +#define MCHP_PCR_PWM7 (BIT(8) + 26) +#define MCHP_PCR_PWM6 (BIT(8) + 25) +#define MCHP_PCR_PWM5 (BIT(8) + 24) +#define MCHP_PCR_PWM4 (BIT(8) + 23) +#define MCHP_PCR_PWM3 (BIT(8) + 22) +#define MCHP_PCR_PWM2 (BIT(8) + 21) +#define MCHP_PCR_PWM1 (BIT(8) + 20) +#define MCHP_PCR_TACH2 (BIT(8) + 12) +#define MCHP_PCR_TACH1 (BIT(8) + 11) +#define MCHP_PCR_I2C0 (BIT(8) + 10) +#define MCHP_PCR_WDT (BIT(8) + 9) +#define MCHP_PCR_CPU (BIT(8) + 8) +#define MCHP_PCR_TFDP (BIT(8) + 7) +#define MCHP_PCR_DMA (BIT(8) + 6) +#define MCHP_PCR_PMC (BIT(8) + 5) +#define MCHP_PCR_PWM0 (BIT(8) + 4) +#define MCHP_PCR_TACH0 (BIT(8) + 2) +#define MCHP_PCR_PECI (BIT(8) + 1) +#define MCHP_PCR_ECIA (BIT(8) + 0) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN1_BTMR16_1 (1 << 31) -#define MCHP_PCR_SLP_EN1_BTMR16_0 (1 << 30) -#define MCHP_PCR_SLP_EN1_ECS (1 << 29) +#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31) +#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30) +#define MCHP_PCR_SLP_EN1_ECS BIT(29) /* bit[28] reserved */ -#define MCHP_PCR_SLP_EN1_PWM_ALL ((1 << 4) + (0xff << 20)) -#define MCHP_PCR_SLP_EN1_PWM8 (1 << 27) -#define MCHP_PCR_SLP_EN1_PWM7 (1 << 26) -#define MCHP_PCR_SLP_EN1_PWM6 (1 << 25) -#define MCHP_PCR_SLP_EN1_PWM5 (1 << 24) -#define MCHP_PCR_SLP_EN1_PWM4 (1 << 23) -#define MCHP_PCR_SLP_EN1_PWM3 (1 << 22) -#define MCHP_PCR_SLP_EN1_PWM2 (1 << 21) -#define MCHP_PCR_SLP_EN1_PWM1 (1 << 20) +#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20)) +#define MCHP_PCR_SLP_EN1_PWM8 BIT(27) +#define MCHP_PCR_SLP_EN1_PWM7 BIT(26) +#define MCHP_PCR_SLP_EN1_PWM6 BIT(25) +#define MCHP_PCR_SLP_EN1_PWM5 BIT(24) +#define MCHP_PCR_SLP_EN1_PWM4 BIT(23) +#define MCHP_PCR_SLP_EN1_PWM3 BIT(22) +#define MCHP_PCR_SLP_EN1_PWM2 BIT(21) +#define MCHP_PCR_SLP_EN1_PWM1 BIT(20) /* bits[19:13] reserved */ -#define MCHP_PCR_SLP_EN1_TACH2 (1 << 12) -#define MCHP_PCR_SLP_EN1_TACH1 (1 << 11) -#define MCHP_PCR_SLP_EN1_I2C0 (1 << 10) -#define MCHP_PCR_SLP_EN1_WDT (1 << 9) -#define MCHP_PCR_SLP_EN1_CPU (1 << 8) -#define MCHP_PCR_SLP_EN1_TFDP (1 << 7) -#define MCHP_PCR_SLP_EN1_DMA (1 << 6) -#define MCHP_PCR_SLP_EN1_PMC (1 << 5) -#define MCHP_PCR_SLP_EN1_PWM0 (1 << 4) +#define MCHP_PCR_SLP_EN1_TACH2 BIT(12) +#define MCHP_PCR_SLP_EN1_TACH1 BIT(11) +#define MCHP_PCR_SLP_EN1_I2C0 BIT(10) +#define MCHP_PCR_SLP_EN1_WDT BIT(9) +#define MCHP_PCR_SLP_EN1_CPU BIT(8) +#define MCHP_PCR_SLP_EN1_TFDP BIT(7) +#define MCHP_PCR_SLP_EN1_DMA BIT(6) +#define MCHP_PCR_SLP_EN1_PMC BIT(5) +#define MCHP_PCR_SLP_EN1_PWM0 BIT(4) /* bit[3] reserved */ -#define MCHP_PCR_SLP_EN1_TACH0 (1 << 2) -#define MCHP_PCR_SLP_EN1_PECI (1 << 1) -#define MCHP_PCR_SLP_EN1_ECIA (1 << 0) +#define MCHP_PCR_SLP_EN1_TACH0 BIT(2) +#define MCHP_PCR_SLP_EN1_PECI BIT(1) +#define MCHP_PCR_SLP_EN1_ECIA BIT(0) /* all sleep enable 1 bits */ #define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff /* @@ -176,25 +176,25 @@ /* Command all blocks to sleep */ /* bits[31:27] reserved */ -#define MCHP_PCR_SLP_EN2_P80CAP1 (1 << 26) -#define MCHP_PCR_SLP_EN2_P80CAP0 (1 << 25) +#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26) +#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25) /* bit[24] reserved */ -#define MCHP_PCR_SLP_EN2_ACPI_EC4 (1 << 23) -#define MCHP_PCR_SLP_EN2_ACPI_EC3 (1 << 22) -#define MCHP_PCR_SLP_EN2_ACPI_EC2 (1 << 21) +#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23) +#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22) +#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21) /* bit[20] reserved */ -#define MCHP_PCR_SLP_EN2_ESPI (1 << 19) -#define MCHP_PCR_SLP_EN2_RTC (1 << 18) -#define MCHP_PCR_SLP_EN2_MAILBOX (1 << 17) -#define MCHP_PCR_SLP_EN2_MIF8042 (1 << 16) -#define MCHP_PCR_SLP_EN2_ACPI_PM1 (1 << 15) -#define MCHP_PCR_SLP_EN2_ACPI_EC1 (1 << 14) -#define MCHP_PCR_SLP_EN2_ACPI_EC0 (1 << 13) -#define MCHP_PCR_SLP_EN2_GCFG (1 << 12) +#define MCHP_PCR_SLP_EN2_ESPI BIT(19) +#define MCHP_PCR_SLP_EN2_RTC BIT(18) +#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17) +#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16) +#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15) +#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14) +#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13) +#define MCHP_PCR_SLP_EN2_GCFG BIT(12) /* bits[11:3] reserved */ -#define MCHP_PCR_SLP_EN2_UART1 (1 << 2) -#define MCHP_PCR_SLP_EN2_UART0 (1 << 1) -#define MCHP_PCR_SLP_EN2_LPC (1 << 0) +#define MCHP_PCR_SLP_EN2_UART1 BIT(2) +#define MCHP_PCR_SLP_EN2_UART0 BIT(1) +#define MCHP_PCR_SLP_EN2_LPC BIT(0) /* all sleep enable 2 bits */ #define MCHP_PCR_SLP_EN2_SLEEP 0x07ffffff @@ -228,35 +228,35 @@ #define MCHP_PCR_ADC ((3 << 8) + 3) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN3_PWM9 (1 << 31) -#define MCHP_PCR_SLP_EN3_CCT0 (1 << 30) -#define MCHP_PCR_SLP_EN3_HTMR1 (1 << 29) -#define MCHP_PCR_SLP_EN3_AESHASH (1 << 28) -#define MCHP_PCR_SLP_EN3_RNG (1 << 27) -#define MCHP_PCR_SLP_EN3_PKE (1 << 26) -#define MCHP_PCR_SLP_EN3_LED3 (1 << 25) -#define MCHP_PCR_SLP_EN3_BTMR32_1 (1 << 24) -#define MCHP_PCR_SLP_EN3_BTMR32_0 (1 << 23) -#define MCHP_PCR_SLP_EN3_BTMR16_3 (1 << 22) -#define MCHP_PCR_SLP_EN3_BTMR16_2 (1 << 21) -#define MCHP_PCR_SLP_EN3_GPSPI1 (1 << 20) -#define MCHP_PCR_SLP_EN3_BCM0 (1 << 19) -#define MCHP_PCR_SLP_EN3_LED2 (1 << 18) -#define MCHP_PCR_SLP_EN3_LED1 (1 << 17) -#define MCHP_PCR_SLP_EN3_LED0 (1 << 16) -#define MCHP_PCR_SLP_EN3_I2C3 (1 << 15) -#define MCHP_PCR_SLP_EN3_I2C2 (1 << 14) -#define MCHP_PCR_SLP_EN3_I2C1 (1 << 13) -#define MCHP_PCR_SLP_EN3_RPMPWM0 (1 << 12) -#define MCHP_PCR_SLP_EN3_KEYSCAN (1 << 11) -#define MCHP_PCR_SLP_EN3_HTMR0 (1 << 10) -#define MCHP_PCR_SLP_EN3_GPSPI0 (1 << 9) +#define MCHP_PCR_SLP_EN3_PWM9 BIT(31) +#define MCHP_PCR_SLP_EN3_CCT0 BIT(30) +#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29) +#define MCHP_PCR_SLP_EN3_AESHASH BIT(28) +#define MCHP_PCR_SLP_EN3_RNG BIT(27) +#define MCHP_PCR_SLP_EN3_PKE BIT(26) +#define MCHP_PCR_SLP_EN3_LED3 BIT(25) +#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24) +#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23) +#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22) +#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21) +#define MCHP_PCR_SLP_EN3_GPSPI1 BIT(20) +#define MCHP_PCR_SLP_EN3_BCM0 BIT(19) +#define MCHP_PCR_SLP_EN3_LED2 BIT(18) +#define MCHP_PCR_SLP_EN3_LED1 BIT(17) +#define MCHP_PCR_SLP_EN3_LED0 BIT(16) +#define MCHP_PCR_SLP_EN3_I2C3 BIT(15) +#define MCHP_PCR_SLP_EN3_I2C2 BIT(14) +#define MCHP_PCR_SLP_EN3_I2C1 BIT(13) +#define MCHP_PCR_SLP_EN3_RPMPWM0 BIT(12) +#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11) +#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10) +#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9) /* bit[8] reserved */ -#define MCHP_PCR_SLP_EN3_PS2_2 (1 << 7) -#define MCHP_PCR_SLP_EN3_PS2_1 (1 << 6) -#define MCHP_PCR_SLP_EN3_PS2_0 (1 << 5) +#define MCHP_PCR_SLP_EN3_PS2_2 BIT(7) +#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6) +#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5) /* bit[4] reserved */ -#define MCHP_PCR_SLP_EN3_ADC (1 << 3) +#define MCHP_PCR_SLP_EN3_ADC BIT(3) /* bits[2:0] reserved */ /* all sleep enable 3 bits */ #define MCHP_PCR_SLP_EN3_SLEEP 0xfffffeed @@ -281,23 +281,23 @@ #define MCHP_PCR_PWM10 ((4 << 8) + 0) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN4_FJCL (1 << 15) -#define MCHP_PCR_SLP_EN4_PSPI (1 << 14) -#define MCHP_PCR_SLP_EN4_PROCHOT (1 << 13) -#define MCHP_PCR_SLP_EN4_RCID2 (1 << 12) -#define MCHP_PCR_SLP_EN4_RCID1 (1 << 11) -#define MCHP_PCR_SLP_EN4_RCID0 (1 << 10) -#define MCHP_PCR_SLP_EN4_BCM1 (1 << 9) -#define MCHP_PCR_SLP_EN4_QMSPI (1 << 8) -#define MCHP_PCR_SLP_EN4_RPMPWM1 (1 << 7) -#define MCHP_PCR_SLP_EN4_RTMR (1 << 6) -#define MCHP_PCR_SLP_EN4_CNT16_3 (1 << 5) -#define MCHP_PCR_SLP_EN4_CNT16_2 (1 << 4) -#define MCHP_PCR_SLP_EN4_CNT16_1 (1 << 3) -#define MCHP_PCR_SLP_EN4_CNT16_0 (1 << 2) +#define MCHP_PCR_SLP_EN4_FJCL BIT(15) +#define MCHP_PCR_SLP_EN4_PSPI BIT(14) +#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13) +#define MCHP_PCR_SLP_EN4_RCID2 BIT(12) +#define MCHP_PCR_SLP_EN4_RCID1 BIT(11) +#define MCHP_PCR_SLP_EN4_RCID0 BIT(10) +#define MCHP_PCR_SLP_EN4_BCM1 BIT(9) +#define MCHP_PCR_SLP_EN4_QMSPI BIT(8) +#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7) +#define MCHP_PCR_SLP_EN4_RTMR BIT(6) +#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5) +#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4) +#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3) +#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2) #define MCHP_PCR_SLP_EN4_PWM_ALL (3 << 0) -#define MCHP_PCR_SLP_EN4_PWM11 (1 << 1) -#define MCHP_PCR_SLP_EN4_PWM10 (1 << 0) +#define MCHP_PCR_SLP_EN4_PWM11 BIT(1) +#define MCHP_PCR_SLP_EN4_PWM10 BIT(0) /* all sleep enable 4 bits */ #define MCHP_PCR_SLP_EN4_SLEEP 0x0000ffff @@ -314,17 +314,17 @@ /* Bit definitions for MCHP_PCR_SLP_EN2/CLK_REQ2/RST_EN2 */ /* Bit definitions for MCHP_PCR_SLP_EN3/CLK_REQ3/RST_EN3 */ -#define MCHP_PCR_SLP_EN1_PKE (1 << 26) -#define MCHP_PCR_SLP_EN1_NDRNG (1 << 27) -#define MCHP_PCR_SLP_EN1_AES_SHA (1 << 28) +#define MCHP_PCR_SLP_EN1_PKE BIT(26) +#define MCHP_PCR_SLP_EN1_NDRNG BIT(27) +#define MCHP_PCR_SLP_EN1_AES_SHA BIT(28) #define MCHP_PCR_SLP_EN1_ALL_CRYPTO (0x07 << 26) /* Bit definitions for MCHP_PCR_SLP_EN4/CLK_REQ4/RST_EN4 */ /* Bit defines for MCHP_PCR_PWR_RST_STS */ -#define MCHP_PWR_RST_STS_VTR (1 << 6) -#define MCHP_PWR_RST_STS_VBAT (1 << 5) +#define MCHP_PWR_RST_STS_VTR BIT(6) +#define MCHP_PWR_RST_STS_VBAT BIT(5) /* Bit defines for MCHP_PCR_PWR_RST_CTL */ #define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8 @@ -333,7 +333,7 @@ /* Bit defines for MCHP_PCR_SYS_RST */ -#define MCHP_PCR_SYS_SOFT_RESET (1 << 8) +#define MCHP_PCR_SYS_SOFT_RESET BIT(8) /* TFDP */ @@ -554,7 +554,7 @@ #define MCHP_UART_GIRQ_BIT(x) (1ul << (x)) /* Bit defines for MCHP_UARTx_LSR */ -#define MCHP_LSR_TX_EMPTY (1 << 5) +#define MCHP_LSR_TX_EMPTY BIT(5) /* GPIO */ @@ -580,7 +580,7 @@ * Example: GPIO043, Control 1 register address = 0x4008108c * port/bank = 0x23 >> 5 = 1 * id = 0x23 & 0x1F = 0x03 - * Control 1 Address = 0x40081000 + (((1 << 5) + 0x03) << 2) = 0x4008108c + * Control 1 Address = 0x40081000 + ((BIT(5) + 0x03) << 2) = 0x4008108c * * Example: GPIO235, Control 1 register address = 0x40081274 * port/bank = 0x9d >> 5 = 4 @@ -641,7 +641,7 @@ #define MCHP_GPIO_CTRL_FUNC_1 (1 << 12) #define MCHP_GPIO_CTRL_FUNC_2 (2 << 12) #define MCHP_GPIO_CTRL_FUNC_3 (3 << 12) -#define MCHP_GPIO_CTRL_OUT_LVL (1 << 16) +#define MCHP_GPIO_CTRL_OUT_LVL BIT(16) /* GPIO Parallel Input and Output registers. * gpio_bank in [0, 5] @@ -705,11 +705,11 @@ #define MCHP_VBAT_VWIRE_BACKUP 30 /* Bit definition for MCHP_VBAT_STS */ -#define MCHP_VBAT_STS_SOFTRESET (1 << 2) -#define MCHP_VBAT_STS_RESETI (1 << 4) -#define MCHP_VBAT_STS_WDT (1 << 5) -#define MCHP_VBAT_STS_SYSRESETREQ (1 << 6) -#define MCHP_VBAT_STS_VBAT_RST (1 << 7) +#define MCHP_VBAT_STS_SOFTRESET BIT(2) +#define MCHP_VBAT_STS_RESETI BIT(4) +#define MCHP_VBAT_STS_WDT BIT(5) +#define MCHP_VBAT_STS_SYSRESETREQ BIT(6) +#define MCHP_VBAT_STS_VBAT_RST BIT(7) #define MCHP_VBAT_STS_ANY_RST (0xF4u) /* Bit definitions for MCHP_VBAT_CE */ @@ -1326,9 +1326,9 @@ enum MCHP_i2c_port { ((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17) /* Bits in MCHP_QMSPI0_EXE */ -#define MCHP_QMSPI_EXE_START (1 << 0) -#define MCHP_QMSPI_EXE_STOP (1 << 1) -#define MCHP_QMSPI_EXE_CLR_FIFOS (1 << 2) +#define MCHP_QMSPI_EXE_START BIT(0) +#define MCHP_QMSPI_EXE_STOP BIT(1) +#define MCHP_QMSPI_EXE_CLR_FIFOS BIT(2) /* MCHP QMSPI FIFO Sizes */ #define MCHP_QMSPI_TX_FIFO_LEN 8 @@ -1982,30 +1982,30 @@ enum dma_channel { /* Bits for DMA Main Control */ -#define MCHP_DMA_MAIN_CTRL_ACT (1 << 0) -#define MCHP_DMA_MAIN_CTRL_SRST (1 << 1) +#define MCHP_DMA_MAIN_CTRL_ACT BIT(0) +#define MCHP_DMA_MAIN_CTRL_SRST BIT(1) /* Bits for DMA channel regs */ -#define MCHP_DMA_ACT_EN (1 << 0) +#define MCHP_DMA_ACT_EN BIT(0) /* DMA Channel Control */ -#define MCHP_DMA_ABORT (1 << 25) -#define MCHP_DMA_SW_GO (1 << 24) +#define MCHP_DMA_ABORT BIT(25) +#define MCHP_DMA_SW_GO BIT(24) #define MCHP_DMA_XFER_SIZE_MASK (7ul << 20) #define MCHP_DMA_XFER_SIZE(x) ((x) << 20) -#define MCHP_DMA_DIS_HW_FLOW (1 << 19) -#define MCHP_DMA_INC_DEV (1 << 17) -#define MCHP_DMA_INC_MEM (1 << 16) +#define MCHP_DMA_DIS_HW_FLOW BIT(19) +#define MCHP_DMA_INC_DEV BIT(17) +#define MCHP_DMA_INC_MEM BIT(16) #define MCHP_DMA_DEV(x) ((x) << 9) #define MCHP_DMA_DEV_MASK0 (0x7f) #define MCHP_DMA_DEV_MASK (0x7f << 9) -#define MCHP_DMA_TO_DEV (1 << 8) -#define MCHP_DMA_DONE (1 << 2) -#define MCHP_DMA_RUN (1 << 0) +#define MCHP_DMA_TO_DEV BIT(8) +#define MCHP_DMA_DONE BIT(2) +#define MCHP_DMA_RUN BIT(0) /* DMA Channel Status */ -#define MCHP_DMA_STS_ALU_DONE (1 << 3) -#define MCHP_DMA_STS_DONE (1 << 2) -#define MCHP_DMA_STS_HWFL_ERR (1 << 1) -#define MCHP_DMA_STS_BUS_ERR (1 << 0) +#define MCHP_DMA_STS_ALU_DONE BIT(3) +#define MCHP_DMA_STS_DONE BIT(2) +#define MCHP_DMA_STS_HWFL_ERR BIT(1) +#define MCHP_DMA_STS_BUS_ERR BIT(0) /* * Peripheral device DMA Device ID's for bits [15:9] diff --git a/chip/mchp/spi_chip.h b/chip/mchp/spi_chip.h index 7d273e5155..75973e4a78 100644 --- a/chip/mchp/spi_chip.h +++ b/chip/mchp/spi_chip.h @@ -36,7 +36,7 @@ #define GPSPI_CLASS0 1 #define QMSPI_CLASS (0 << 4) -#define GPSPI_CLASS (1 << 4) +#define GPSPI_CLASS BIT(4) #define QMSPI_CTRL0 0 #define GPSPI_CTRL0 0 diff --git a/chip/mchp/uart.c b/chip/mchp/uart.c index adeea5a31c..0f8bd62db8 100644 --- a/chip/mchp/uart.c +++ b/chip/mchp/uart.c @@ -30,7 +30,7 @@ int uart_init_done(void) void uart_tx_start(void) { /* If interrupt is already enabled, nothing to do */ - if (MCHP_UART_IER(0) & (1 << 1)) + if (MCHP_UART_IER(0) & BIT(1)) return; /* Do not allow deep sleep while transmit in progress */ @@ -42,13 +42,13 @@ void uart_tx_start(void) * UART where the FIFO only triggers the interrupt when its * threshold is _crossed_, not just met. */ - MCHP_UART_IER(0) |= (1 << 1); + MCHP_UART_IER(0) |= BIT(1); task_trigger_irq(MCHP_IRQ_UART0); } void uart_tx_stop(void) { - MCHP_UART_IER(0) &= ~(1 << 1); + MCHP_UART_IER(0) &= ~BIT(1); /* Re-allow deep sleep */ enable_sleep(SLEEP_MASK_UART); @@ -79,7 +79,7 @@ int uart_tx_in_progress(void) int uart_rx_available(void) { - return MCHP_UART_LSR(0) & (1 << 0); + return MCHP_UART_LSR(0) & BIT(0); } void uart_write_char(char c) @@ -99,7 +99,7 @@ int uart_read_char(void) static void uart_clear_rx_fifo(int channel) { - MCHP_UART_FCR(0) = (1 << 0) | (1 << 1); + MCHP_UART_FCR(0) = BIT(0) | BIT(1); } void uart_disable_interrupt(void) @@ -131,31 +131,31 @@ void uart_init(void) MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_UART0); /* Set UART to reset on VCC1_RESET instead of nSIO_RESET */ - MCHP_UART_CFG(0) &= ~(1 << 1); + MCHP_UART_CFG(0) &= ~BIT(1); /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ /* Set CLK_SRC = 0 */ - MCHP_UART_CFG(0) &= ~(1 << 0); + MCHP_UART_CFG(0) &= ~BIT(0); /* Set DLAB = 1 */ - MCHP_UART_LCR(0) |= (1 << 7); + MCHP_UART_LCR(0) |= BIT(7); /* PBRG0/PBRG1 */ MCHP_UART_PBRG0(0) = 1; MCHP_UART_PBRG1(0) = 0; /* Set DLAB = 0 */ - MCHP_UART_LCR(0) &= ~(1 << 7); + MCHP_UART_LCR(0) &= ~BIT(7); /* Set word length to 8-bit */ - MCHP_UART_LCR(0) |= (1 << 0) | (1 << 1); + MCHP_UART_LCR(0) |= BIT(0) | BIT(1); /* Enable FIFO */ - MCHP_UART_FCR(0) = (1 << 0); + MCHP_UART_FCR(0) = BIT(0); /* Activate UART */ - MCHP_UART_ACT(0) |= (1 << 0); + MCHP_UART_ACT(0) |= BIT(0); gpio_config_module(MODULE_UART, 1); @@ -163,8 +163,8 @@ void uart_init(void) * Enable interrupts for UART0. */ uart_clear_rx_fifo(0); - MCHP_UART_IER(0) |= (1 << 0); - MCHP_UART_MCR(0) |= (1 << 3); + MCHP_UART_IER(0) |= BIT(0); + MCHP_UART_MCR(0) |= BIT(3); MCHP_INT_ENABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0); task_enable_irq(MCHP_IRQ_UART0); @@ -185,13 +185,13 @@ void uart_enter_dsleep(void) gpio_reset(GPIO_UART0_RX); /* power-down/de-activate UART0 */ - MCHP_UART_ACT(0) &= ~(1 << 0); + MCHP_UART_ACT(0) &= ~BIT(0); /* clear interrupt enable for UART0 */ MCHP_INT_DISABLE(MCHP_UART_GIRQ) = MCHP_UART_GIRQ_BIT(0); /* Clear pending interrupts on GPIO_UART0_RX(GPIO105, girq=9, bit=5) */ - MCHP_INT_SOURCE(9) = (1 << 5); + MCHP_INT_SOURCE(9) = BIT(5); /* Enable GPIO interrupts on the UART0 RX pin. */ gpio_enable_interrupt(GPIO_UART0_RX); @@ -207,7 +207,7 @@ void uart_exit_dsleep(void) * Note: we can't disable this interrupt if it has already fired * because then the IRQ will not run at all. */ - if (!((1 << 5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */ + if (!(BIT(5) & MCHP_INT_SOURCE(9))) /* if edge interrupt */ gpio_disable_interrupt(GPIO_UART0_RX); /* Configure UART0 pins for use in UART peripheral. */ @@ -220,7 +220,7 @@ void uart_exit_dsleep(void) task_enable_irq(MCHP_IRQ_UART0); /* NVIC interrupt for UART = 40 */ /* power-up/activate UART0 */ - MCHP_UART_ACT(0) |= (1 << 0); + MCHP_UART_ACT(0) |= BIT(0); } void uart_deepsleep_interrupt(enum gpio_signal signal) diff --git a/chip/mchp/watchdog.c b/chip/mchp/watchdog.c index 03edeb414e..0533155e08 100644 --- a/chip/mchp/watchdog.c +++ b/chip/mchp/watchdog.c @@ -17,9 +17,9 @@ void watchdog_reload(void) #ifdef CONFIG_WATCHDOG_HELP /* Reload the auxiliary timer */ - MCHP_TMR16_CTL(0) &= ~(1 << 5); + MCHP_TMR16_CTL(0) &= ~BIT(5); MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MCHP_TMR16_CTL(0) |= 1 << 5; + MCHP_TMR16_CTL(0) |= BIT(5); #endif } DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); @@ -38,10 +38,10 @@ int watchdog_init(void) MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_BTMR16_0); /* Stop the auxiliary timer if it's running */ - MCHP_TMR16_CTL(0) &= ~(1 << 5); + MCHP_TMR16_CTL(0) &= ~BIT(5); /* Enable auxiliary timer */ - MCHP_TMR16_CTL(0) |= 1 << 0; + MCHP_TMR16_CTL(0) |= BIT(0); val = MCHP_TMR16_CTL(0); @@ -49,10 +49,10 @@ int watchdog_init(void) val = (val & 0xffff) | (47999 << 16); /* No auto restart */ - val &= ~(1 << 3); + val &= ~BIT(3); /* Count down */ - val &= ~(1 << 2); + val &= ~BIT(2); MCHP_TMR16_CTL(0) = val; @@ -63,7 +63,7 @@ int watchdog_init(void) /* Load and start the auxiliary timer */ MCHP_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MCHP_TMR16_CNT(0) |= 1 << 5; + MCHP_TMR16_CNT(0) |= BIT(5); #endif /* Clear WDT PCR sleep enable */ @@ -75,7 +75,7 @@ int watchdog_init(void) /* Start watchdog */ #ifdef CONFIG_CHIPSET_DEBUG /* WDT will not count if JTAG TRST# is pulled high by JTAG cable */ - MCHP_WDG_CTL = (1 << 4) | (1 << 0); + MCHP_WDG_CTL = BIT(4) | BIT(0); #else MCHP_WDG_CTL |= 1; #endif diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c index a1210fa274..9026cf8a2e 100644 --- a/chip/mec1322/adc.c +++ b/chip/mec1322/adc.c @@ -30,7 +30,7 @@ static int start_single_and_wait(int timeout) task_waiting = task_get_current(); /* Start conversion */ - MEC1322_ADC_CTRL |= 1 << 1; + MEC1322_ADC_CTRL |= BIT(1); /* Wait for interrupt */ event = task_wait_event(timeout); @@ -60,12 +60,12 @@ int adc_read_channel(enum adc_channel ch) static void adc_init(void) { /* Activate ADC module */ - MEC1322_ADC_CTRL |= 1 << 0; + MEC1322_ADC_CTRL |= BIT(0); /* Enable interrupt */ task_waiting = TASK_ID_INVALID; - MEC1322_INT_ENABLE(17) |= 1 << 10; - MEC1322_INT_BLK_EN |= 1 << 17; + MEC1322_INT_ENABLE(17) |= BIT(10); + MEC1322_INT_BLK_EN |= BIT(17); task_enable_irq(MEC1322_IRQ_ADC_SNGL); } DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); @@ -73,7 +73,7 @@ DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); void adc_interrupt(void) { /* Clear interrupt status bit */ - MEC1322_ADC_CTRL |= 1 << 7; + MEC1322_ADC_CTRL |= BIT(7); if (task_waiting != TASK_ID_INVALID) task_wake(task_waiting); diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c index d86f1bc5a7..3f58ef086c 100644 --- a/chip/mec1322/clock.c +++ b/chip/mec1322/clock.c @@ -103,8 +103,8 @@ DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1); */ static void htimer_init(void) { - MEC1322_INT_BLK_EN |= 1 << 17; - MEC1322_INT_ENABLE(17) |= 1 << 20; /* GIRQ=17, aggregator bit = 20 */ + MEC1322_INT_BLK_EN |= BIT(17); + MEC1322_INT_ENABLE(17) |= BIT(20); /* GIRQ=17, aggregator bit = 20 */ MEC1322_HTIMER_PRELOAD = 0; /* disable at beginning */ task_enable_irq(MEC1322_IRQ_HTIMER); diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c index b354fea2a4..34617c92bc 100644 --- a/chip/mec1322/dma.c +++ b/chip/mec1322/dma.c @@ -27,8 +27,8 @@ void dma_disable(enum dma_channel channel) { mec1322_dma_chan_t *chan = dma_get_channel(channel); - if (chan->ctrl & (1 << 0)) - chan->ctrl &= ~(1 << 0); + if (chan->ctrl & BIT(0)) + chan->ctrl &= ~BIT(0); if (chan->act == 1) chan->act = 0; @@ -42,9 +42,9 @@ void dma_disable_all(void) for (ch = 0; ch < MEC1322_DMAC_COUNT; ch++) { mec1322_dma_chan_t *chan = dma_get_channel(ch); /* Abort any current transfer. */ - chan->ctrl |= (1 << 25); + chan->ctrl |= BIT(25); /* Disable the channel. */ - chan->ctrl &= ~(1 << 0); + chan->ctrl &= ~BIT(0); chan->act = 0; } @@ -69,8 +69,8 @@ static void prepare_channel(mec1322_dma_chan_t *chan, unsigned count, { int xfer_size = (flags >> 20) & 0x7; - if (chan->ctrl & (1 << 0)) - chan->ctrl &= ~(1 << 0); + if (chan->ctrl & BIT(0)) + chan->ctrl &= ~BIT(0); chan->act |= 0x1; chan->dev = (uint32_t)periph; diff --git a/chip/mec1322/fan.c b/chip/mec1322/fan.c index 9636bc816e..0f40ba22be 100644 --- a/chip/mec1322/fan.c +++ b/chip/mec1322/fan.c @@ -81,15 +81,15 @@ int fan_get_duty(int ch) int fan_get_rpm_mode(int ch) { - return !!(MEC1322_FAN_CFG1 & (1 << 7)); + return !!(MEC1322_FAN_CFG1 & BIT(7)); } void fan_set_rpm_mode(int ch, int rpm_mode) { if (rpm_mode) - MEC1322_FAN_CFG1 |= 1 << 7; + MEC1322_FAN_CFG1 |= BIT(7); else - MEC1322_FAN_CFG1 &= ~(1 << 7); + MEC1322_FAN_CFG1 &= ~BIT(7); clear_status(); } @@ -117,7 +117,7 @@ enum fan_status fan_get_status(int ch) { uint8_t sts = MEC1322_FAN_STATUS; - if (sts & ((1 << 5) | (1 << 1))) + if (sts & (BIT(5) | BIT(1))) return FAN_STATUS_FRUSTRATED; if (fan_get_rpm_actual(ch) == 0) return FAN_STATUS_STOPPED; diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c index 4df46dd6d8..c3b62ad583 100644 --- a/chip/mec1322/gpio.c +++ b/chip/mec1322/gpio.c @@ -37,7 +37,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) while (mask) { i = __builtin_ffs(mask) - 1; val = MEC1322_GPIO_CTL(port, i); - val &= ~((1 << 12) | (1 << 13)); + val &= ~(BIT(12) | BIT(13)); /* mux_control = 0 indicates GPIO */ if (func > 0) val |= (func & 0x3) << 12; @@ -57,7 +57,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal) i = GPIO_MASK_TO_NUM(mask); val = MEC1322_GPIO_CTL(gpio_list[signal].port, i); - return (val & (1 << 24)) ? 1 : 0; + return (val & BIT(24)) ? 1 : 0; } void gpio_set_level(enum gpio_signal signal, int value) @@ -70,9 +70,9 @@ void gpio_set_level(enum gpio_signal signal, int value) i = GPIO_MASK_TO_NUM(mask); if (value) - MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= (1 << 16); + MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16); else - MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~(1 << 16); + MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16); } void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) @@ -89,16 +89,16 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) * when changing the line to an output. */ if (flags & GPIO_OPEN_DRAIN) - val |= (1 << 8); + val |= BIT(8); else - val &= ~(1 << 8); + val &= ~BIT(8); if (flags & GPIO_OUTPUT) { - val |= (1 << 9); - val &= ~(1 << 10); + val |= BIT(9); + val &= ~BIT(10); } else { - val &= ~(1 << 9); - val |= (1 << 10); + val &= ~BIT(9); + val |= BIT(10); } /* Handle pullup / pulldown */ @@ -111,9 +111,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* Set up interrupt */ if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) - val |= (1 << 7); + val |= BIT(7); else - val &= ~(1 << 7); + val &= ~BIT(7); val &= ~(0x7 << 4); @@ -130,9 +130,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* Set up level */ if (flags & GPIO_HIGH) - val |= (1 << 16); + val |= BIT(16); else if (flags & GPIO_LOW) - val &= ~(1 << 16); + val &= ~BIT(16); MEC1322_GPIO_CTL(port, i) = val; } diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c index be9ffac1ea..4adaa38516 100644 --- a/chip/mec1322/hwtimer.c +++ b/chip/mec1322/hwtimer.c @@ -17,7 +17,7 @@ void __hw_clock_event_set(uint32_t deadline) { MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) - (0xffffffff - deadline); - MEC1322_TMR32_CTL(1) |= (1 << 5); + MEC1322_TMR32_CTL(1) |= BIT(5); } uint32_t __hw_clock_event_get(void) @@ -27,7 +27,7 @@ uint32_t __hw_clock_event_get(void) void __hw_clock_event_clear(void) { - MEC1322_TMR32_CTL(1) &= ~(1 << 5); + MEC1322_TMR32_CTL(1) &= ~BIT(5); } uint32_t __hw_clock_source_read(void) @@ -37,9 +37,9 @@ uint32_t __hw_clock_source_read(void) void __hw_clock_source_set(uint32_t ts) { - MEC1322_TMR32_CTL(0) &= ~(1 << 5); + MEC1322_TMR32_CTL(0) &= ~BIT(5); MEC1322_TMR32_CNT(0) = 0xffffffff - ts; - MEC1322_TMR32_CTL(0) |= (1 << 5); + MEC1322_TMR32_CTL(0) |= BIT(5); } static void __hw_clock_source_irq(int timer_id) @@ -60,10 +60,10 @@ static void configure_timer(int timer_id) uint32_t val; /* Ensure timer is not running */ - MEC1322_TMR32_CTL(timer_id) &= ~(1 << 5); + MEC1322_TMR32_CTL(timer_id) &= ~BIT(5); /* Enable timer */ - MEC1322_TMR32_CTL(timer_id) |= (1 << 0); + MEC1322_TMR32_CTL(timer_id) |= BIT(0); val = MEC1322_TMR32_CTL(timer_id); @@ -94,16 +94,16 @@ int __hw_clock_source_init(uint32_t start_t) MEC1322_TMR32_CNT(0) = 0xffffffff - start_t; /* Auto restart */ - MEC1322_TMR32_CTL(0) |= (1 << 3); + MEC1322_TMR32_CTL(0) |= BIT(3); /* Start counting in timer 0 */ - MEC1322_TMR32_CTL(0) |= (1 << 5); + MEC1322_TMR32_CTL(0) |= BIT(5); /* Enable interrupt */ task_enable_irq(MEC1322_IRQ_TIMER32_0); task_enable_irq(MEC1322_IRQ_TIMER32_1); - MEC1322_INT_ENABLE(23) |= (1 << 4) | (1 << 5); - MEC1322_INT_BLK_EN |= (1 << 23); + MEC1322_INT_ENABLE(23) |= BIT(4) | BIT(5); + MEC1322_INT_BLK_EN |= BIT(23); return MEC1322_IRQ_TIMER32_1; } diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c index ce3e618c24..2c22256d81 100644 --- a/chip/mec1322/i2c.c +++ b/chip/mec1322/i2c.c @@ -21,22 +21,22 @@ #define I2C_CLOCK 16000000 /* 16 MHz */ /* Status */ -#define STS_NBB (1 << 0) /* Bus busy */ -#define STS_LAB (1 << 1) /* Arbitration lost */ -#define STS_LRB (1 << 3) /* Last received bit */ -#define STS_BER (1 << 4) /* Bus error */ -#define STS_PIN (1 << 7) /* Pending interrupt */ +#define STS_NBB BIT(0) /* Bus busy */ +#define STS_LAB BIT(1) /* Arbitration lost */ +#define STS_LRB BIT(3) /* Last received bit */ +#define STS_BER BIT(4) /* Bus error */ +#define STS_PIN BIT(7) /* Pending interrupt */ /* Control */ -#define CTRL_ACK (1 << 0) /* Acknowledge */ -#define CTRL_STO (1 << 1) /* STOP */ -#define CTRL_STA (1 << 2) /* START */ -#define CTRL_ENI (1 << 3) /* Enable interrupt */ -#define CTRL_ESO (1 << 6) /* Enable serial output */ -#define CTRL_PIN (1 << 7) /* Pending interrupt not */ +#define CTRL_ACK BIT(0) /* Acknowledge */ +#define CTRL_STO BIT(1) /* STOP */ +#define CTRL_STA BIT(2) /* START */ +#define CTRL_ENI BIT(3) /* Enable interrupt */ +#define CTRL_ESO BIT(6) /* Enable serial output */ +#define CTRL_PIN BIT(7) /* Pending interrupt not */ /* Completion */ -#define COMP_IDLE (1 << 29) /* i2c bus is idle */ +#define COMP_IDLE BIT(29) /* i2c bus is idle */ #define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ /* Maximum transfer of a SMBUS block transfer */ @@ -116,21 +116,21 @@ static void configure_controller(int controller, int kbps) configure_controller_speed(controller, kbps); MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_ACK | CTRL_ENI; - MEC1322_I2C_CONFIG(controller) |= 1 << 10; /* ENAB */ + MEC1322_I2C_CONFIG(controller) |= BIT(10); /* ENAB */ /* Enable interrupt */ - MEC1322_I2C_CONFIG(controller) |= 1 << 29; /* ENIDI */ + MEC1322_I2C_CONFIG(controller) |= BIT(29); /* ENIDI */ MEC1322_INT_ENABLE(12) |= (1 << controller); - MEC1322_INT_BLK_EN |= 1 << 12; + MEC1322_INT_BLK_EN |= BIT(12); } static void reset_controller(int controller) { int i; - MEC1322_I2C_CONFIG(controller) |= 1 << 9; + MEC1322_I2C_CONFIG(controller) |= BIT(9); udelay(100); - MEC1322_I2C_CONFIG(controller) &= ~(1 << 9); + MEC1322_I2C_CONFIG(controller) &= ~BIT(9); for (i = 0; i < i2c_ports_used; ++i) if (controller == i2c_port_to_controller(i2c_ports[i].port)) { diff --git a/chip/mec1322/keyboard_raw.c b/chip/mec1322/keyboard_raw.c index 3269af2cf9..a8a1e6b124 100644 --- a/chip/mec1322/keyboard_raw.c +++ b/chip/mec1322/keyboard_raw.c @@ -19,8 +19,8 @@ void keyboard_raw_init(void) gpio_config_module(MODULE_KEYBOARD_SCAN, 1); /* Enable keyboard scan interrupt */ - MEC1322_INT_ENABLE(17) |= 1 << 21; - MEC1322_INT_BLK_EN |= 1 << 17; + MEC1322_INT_ENABLE(17) |= BIT(21); + MEC1322_INT_BLK_EN |= BIT(17); MEC1322_KS_KSI_INT_EN = 0xff; } @@ -32,19 +32,19 @@ void keyboard_raw_task_start(void) test_mockable void keyboard_raw_drive_column(int out) { if (out == KEYBOARD_COLUMN_ALL) { - MEC1322_KS_KSO_SEL = 1 << 5; /* KSEN=0, KSALL=1 */ + MEC1322_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 1); #endif } else if (out == KEYBOARD_COLUMN_NONE) { - MEC1322_KS_KSO_SEL = 1 << 6; /* KSEN=1 */ + MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 0); #endif } else { #ifdef CONFIG_KEYBOARD_COL2_INVERTED if (out == 2) { - MEC1322_KS_KSO_SEL = 1 << 6; /* KSEN=1 */ + MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */ gpio_set_level(GPIO_KBD_KSO2, 1); } else { MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; @@ -84,5 +84,5 @@ DECLARE_IRQ(MEC1322_IRQ_KSC_INT, keyboard_raw_interrupt, 1); int keyboard_raw_is_input_low(int port, int id) { - return (MEC1322_GPIO_CTL(port, id) & (1 << 24)) == 0; + return (MEC1322_GPIO_CTL(port, id) & BIT(24)) == 0; } diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c index 86a4949e17..7dacfc3077 100644 --- a/chip/mec1322/lfw/ec_lfw.c +++ b/chip/mec1322/lfw/ec_lfw.c @@ -48,10 +48,10 @@ void timer_init() uint32_t val = 0; /* Ensure timer is not running */ - MEC1322_TMR32_CTL(0) &= ~(1 << 5); + MEC1322_TMR32_CTL(0) &= ~BIT(5); /* Enable timer */ - MEC1322_TMR32_CTL(0) |= (1 << 0); + MEC1322_TMR32_CTL(0) |= BIT(0); val = MEC1322_TMR32_CTL(0); @@ -67,10 +67,10 @@ void timer_init() MEC1322_TMR32_CNT(0) = 0xffffffff; /* Auto restart */ - MEC1322_TMR32_CTL(0) |= (1 << 3); + MEC1322_TMR32_CTL(0) |= BIT(3); /* Start counting in timer 0 */ - MEC1322_TMR32_CTL(0) |= (1 << 5); + MEC1322_TMR32_CTL(0) |= BIT(5); } @@ -146,7 +146,7 @@ void uart_write_c(char c) uart_write_c('\r'); /* Wait for space in transmit FIFO. */ - while (!(MEC1322_UART_LSR & (1 << 5))) + while (!(MEC1322_UART_LSR & BIT(5))) ; MEC1322_UART_TB = c; } @@ -181,31 +181,31 @@ void jump_to_image(uintptr_t init_addr) void uart_init(void) { /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MEC1322_UART_CFG &= ~(1 << 1); + MEC1322_UART_CFG &= ~BIT(1); /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ /* Set CLK_SRC = 0 */ - MEC1322_UART_CFG &= ~(1 << 0); + MEC1322_UART_CFG &= ~BIT(0); /* Set DLAB = 1 */ - MEC1322_UART_LCR |= (1 << 7); + MEC1322_UART_LCR |= BIT(7); /* PBRG0/PBRG1 */ MEC1322_UART_PBRG0 = 1; MEC1322_UART_PBRG1 = 0; /* Set DLAB = 0 */ - MEC1322_UART_LCR &= ~(1 << 7); + MEC1322_UART_LCR &= ~BIT(7); /* Set word length to 8-bit */ - MEC1322_UART_LCR |= (1 << 0) | (1 << 1); + MEC1322_UART_LCR |= BIT(0) | BIT(1); /* Enable FIFO */ - MEC1322_UART_FCR = (1 << 0); + MEC1322_UART_FCR = BIT(0); /* Activate UART */ - MEC1322_UART_ACT |= (1 << 0); + MEC1322_UART_ACT |= BIT(0); gpio_config_module(MODULE_UART, 1); } diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index 5d2d57f834..829f91a85c 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -190,23 +190,23 @@ static void setup_lpc(void) gpio_config_module(MODULE_LPC, 1); /* Set up interrupt on LRESET# deassert */ - MEC1322_INT_SOURCE(19) = 1 << 1; - MEC1322_INT_ENABLE(19) |= 1 << 1; - MEC1322_INT_BLK_EN |= 1 << 19; + MEC1322_INT_SOURCE(19) = BIT(1); + MEC1322_INT_ENABLE(19) |= BIT(1); + MEC1322_INT_BLK_EN |= BIT(19); task_enable_irq(MEC1322_IRQ_GIRQ19); /* Set up ACPI0 for 0x62/0x66 */ MEC1322_LPC_ACPI_EC0_BAR = 0x00628304; - MEC1322_INT_ENABLE(15) |= 1 << 6; - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= BIT(6); + MEC1322_INT_BLK_EN |= BIT(15); /* Clear STATUS_PROCESSING bit in case it was set during sysjump */ MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING; task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); /* Set up ACPI1 for 0x200/0x204 */ MEC1322_LPC_ACPI_EC1_BAR = 0x02008407; - MEC1322_INT_ENABLE(15) |= 1 << 8; - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= BIT(8); + MEC1322_INT_BLK_EN |= BIT(15); MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; task_enable_irq(MEC1322_IRQ_ACPIEC1_IBF); @@ -214,24 +214,24 @@ static void setup_lpc(void) MEC1322_LPC_8042_BAR = 0x00608104; /* Set up indication of Auxiliary sts */ - MEC1322_8042_KB_CTRL |= 1 << 7; + MEC1322_8042_KB_CTRL |= BIT(7); MEC1322_8042_ACT |= 1; - MEC1322_INT_ENABLE(15) |= ((1 << 13) | (1 << 14)); - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= (BIT(13) | BIT(14)); + MEC1322_INT_BLK_EN |= BIT(15); task_enable_irq(MEC1322_IRQ_8042EM_IBF); task_enable_irq(MEC1322_IRQ_8042EM_OBF); #ifndef CONFIG_KEYBOARD_IRQ_GPIO /* Set up SERIRQ for keyboard */ - MEC1322_8042_KB_CTRL |= (1 << 5); + MEC1322_8042_KB_CTRL |= BIT(5); MEC1322_LPC_SIRQ(1) = 0x01; #endif /* Set up EMI module for memory mapped region, base address 0x800 */ MEC1322_LPC_EMI_BAR = 0x0800800f; - MEC1322_INT_ENABLE(15) |= 1 << 2; - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= BIT(2); + MEC1322_INT_BLK_EN |= BIT(15); task_enable_irq(MEC1322_IRQ_EMI); /* Access data RAM through alias address */ @@ -295,7 +295,7 @@ DECLARE_DEFERRED(lpc_chipset_reset); void girq19_interrupt(void) { /* Check interrupt result for LRESET# trigger */ - if (MEC1322_INT_RESULT(19) & (1 << 1)) { + if (MEC1322_INT_RESULT(19) & BIT(1)) { /* Initialize LPC module when LRESET# is deasserted */ if (!lpc_get_pltrst_asserted()) { setup_lpc(); @@ -313,7 +313,7 @@ void girq19_interrupt(void) lpc_get_pltrst_asserted() ? "" : "de"); /* Clear interrupt source */ - MEC1322_INT_SOURCE(19) = 1 << 1; + MEC1322_INT_SOURCE(19) = BIT(1); } } DECLARE_IRQ(MEC1322_IRQ_GIRQ19, girq19_interrupt, 1); @@ -423,7 +423,7 @@ void kb_ibf_interrupt(void) { if (lpc_keyboard_input_pending()) keyboard_host_write(MEC1322_8042_H2E, - MEC1322_8042_STS & (1 << 3)); + MEC1322_8042_STS & BIT(3)); task_wake(TASK_ID_KEYPROTO); } DECLARE_IRQ(MEC1322_IRQ_8042EM_IBF, kb_ibf_interrupt, 1); @@ -437,12 +437,12 @@ DECLARE_IRQ(MEC1322_IRQ_8042EM_OBF, kb_obf_interrupt, 1); int lpc_keyboard_has_char(void) { - return (MEC1322_8042_STS & (1 << 0)) ? 1 : 0; + return (MEC1322_8042_STS & BIT(0)) ? 1 : 0; } int lpc_keyboard_input_pending(void) { - return (MEC1322_8042_STS & (1 << 1)) ? 1 : 0; + return (MEC1322_8042_STS & BIT(1)) ? 1 : 0; } void lpc_keyboard_put_char(uint8_t chr, int send_irq) @@ -506,7 +506,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c index fa4fd36a4f..df4583ed8b 100644 --- a/chip/mec1322/port80.c +++ b/chip/mec1322/port80.c @@ -31,7 +31,7 @@ static void port_80_interrupt_enable(void) /* Enable the interrupt. */ task_enable_irq(MEC1322_IRQ_TIMER16_1); /* Enable and start the timer. */ - MEC1322_TMR16_CTL(1) |= 1 | (1 << 5); + MEC1322_TMR16_CTL(1) |= 1 | BIT(5); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, port_80_interrupt_enable, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_CHIPSET_RESET, port_80_interrupt_enable, HOOK_PRIO_DEFAULT); @@ -61,9 +61,9 @@ static void port_80_interrupt_init(void) val = MEC1322_TMR16_CTL(1); val = (val & 0xFFFF) | (47 << 16); /* Automatically restart the timer. */ - val |= (1 << 3); + val |= BIT(3); /* The counter should decrement. */ - val &= ~(1 << 2); + val &= ~BIT(2); MEC1322_TMR16_CTL(1) = val; /* Set the reload value(us). */ @@ -73,12 +73,12 @@ static void port_80_interrupt_init(void) MEC1322_TMR16_STS(1) |= 1; /* Clear any pending interrupt. */ - MEC1322_INT_SOURCE(23) = (1 << 1); + MEC1322_INT_SOURCE(23) = BIT(1); /* Enable IRQ vector 23. */ - MEC1322_INT_BLK_EN |= (1 << 23); + MEC1322_INT_BLK_EN |= BIT(23); /* Enable the interrupt. */ MEC1322_TMR16_IEN(1) |= 1; - MEC1322_INT_ENABLE(23) = (1 << 1); + MEC1322_INT_ENABLE(23) = BIT(1); port_80_interrupt_enable(); } @@ -89,7 +89,7 @@ void port_80_interrupt(void) int data; MEC1322_TMR16_STS(1) = 1; /* Ack the interrupt */ - if ((1 << 1) & MEC1322_INT_RESULT(23)) { + if (BIT(1) & MEC1322_INT_RESULT(23)) { data = port_80_read(); if (data != PORT_80_IGNORE) { diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c index 64547490f4..314f92fb6a 100644 --- a/chip/mec1322/pwm.c +++ b/chip/mec1322/pwm.c @@ -67,8 +67,8 @@ static void pwm_configure(int ch, int active_low, int clock_low) * clock_low=1 selects the 100kHz_Clk source */ MEC1322_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ - (active_low ? (1 << 2) : 0) | - (clock_low ? (1 << 1) : 0); + (active_low ? BIT(2) : 0) | + (clock_low ? BIT(1) : 0); } static void pwm_init(void) diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h index c36e72b089..877a48ff7a 100644 --- a/chip/mec1322/registers.h +++ b/chip/mec1322/registers.h @@ -28,10 +28,10 @@ /* Command all blocks to sleep */ #define MEC1322_PCR_EC_SLP_EN_SLEEP 0xe0700ff7 #define MEC1322_PCR_EC_SLP_EN_PWM(n) (1 << ((n) ? (19 + (n)) : 4)) -#define MEC1322_PCR_EC_SLP_EN_PWM3 (1 << 22) -#define MEC1322_PCR_EC_SLP_EN_PWM2 (1 << 21) -#define MEC1322_PCR_EC_SLP_EN_PWM1 (1 << 20) -#define MEC1322_PCR_EC_SLP_EN_PWM0 (1 << 4) +#define MEC1322_PCR_EC_SLP_EN_PWM3 BIT(22) +#define MEC1322_PCR_EC_SLP_EN_PWM2 BIT(21) +#define MEC1322_PCR_EC_SLP_EN_PWM1 BIT(20) +#define MEC1322_PCR_EC_SLP_EN_PWM0 BIT(4) /* Allow all blocks to request clocks */ #define MEC1322_PCR_EC_SLP_EN_WAKE (~0xe0700ff7) #define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc) @@ -59,8 +59,8 @@ #define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48) /* Bit defines for MEC1322_PCR_CHIP_PWR_RST */ -#define MEC1322_PWR_RST_STS_VCC1 (1 << 6) -#define MEC1322_PWR_RST_STS_VBAT (1 << 5) +#define MEC1322_PWR_RST_STS_VCC1 BIT(6) +#define MEC1322_PWR_RST_STS_VBAT BIT(5) /* EC Subsystem */ #define MEC1322_EC_BASE 0x4000fc00 @@ -106,7 +106,7 @@ #define MEC1322_UART_SCR REG8(MEC1322_UART_RUNTIME_BASE + 0x7) /* Bit defines for MEC1322_UART_LSR */ -#define MEC1322_LSR_TX_EMPTY (1 << 5) +#define MEC1322_LSR_TX_EMPTY BIT(5) /* GPIO */ #define MEC1322_GPIO_BASE 0x40081000 @@ -152,7 +152,7 @@ static inline uintptr_t gpio_port_base(int port_id) #define MEC1322_VBAT_RAM(x) REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x)) /* Bit definition for MEC1322_VBAT_STS */ -#define MEC1322_VBAT_STS_WDT (1 << 5) +#define MEC1322_VBAT_STS_WDT BIT(5) /* Miscellaneous firmware control fields * scratch pad index cannot be more than 16 as @@ -416,14 +416,14 @@ typedef volatile struct mec1322_dma_regs mec1322_dma_regs_t; #define MEC1322_DMA_REGS ((mec1322_dma_regs_t *)MEC1322_DMA_BASE) /* Bits for DMA channel regs */ -#define MEC1322_DMA_ACT_EN (1 << 0) +#define MEC1322_DMA_ACT_EN BIT(0) #define MEC1322_DMA_XFER_SIZE(x) ((x) << 20) -#define MEC1322_DMA_INC_DEV (1 << 17) -#define MEC1322_DMA_INC_MEM (1 << 16) +#define MEC1322_DMA_INC_DEV BIT(17) +#define MEC1322_DMA_INC_MEM BIT(16) #define MEC1322_DMA_DEV(x) ((x) << 9) -#define MEC1322_DMA_TO_DEV (1 << 8) -#define MEC1322_DMA_DONE (1 << 2) -#define MEC1322_DMA_RUN (1 << 0) +#define MEC1322_DMA_TO_DEV BIT(8) +#define MEC1322_DMA_DONE BIT(2) +#define MEC1322_DMA_RUN BIT(0) /* IRQ Numbers */ diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c index 705a95c44e..f7211f7289 100644 --- a/chip/mec1322/spi.c +++ b/chip/mec1322/spi.c @@ -83,14 +83,14 @@ int spi_transaction_async(const struct spi_device_t *spi_device, gpio_set_level(spi_device->gpio_cs, 0); /* Disable auto read */ - MEC1322_SPI_CR(port) &= ~(1 << 5); + MEC1322_SPI_CR(port) &= ~BIT(5); ret = spi_tx(port, txdata, txlen); if (ret != EC_SUCCESS) return ret; /* Enable auto read */ - MEC1322_SPI_CR(port) |= 1 << 5; + MEC1322_SPI_CR(port) |= BIT(5); if (rxlen != 0) { dma_start_rx(&spi_rx_option[port], rxlen, rxdata); @@ -108,7 +108,7 @@ int spi_transaction_flush(const struct spi_device_t *spi_device) timestamp_t deadline; /* Disable auto read */ - MEC1322_SPI_CR(port) &= ~(1 << 5); + MEC1322_SPI_CR(port) &= ~BIT(5); deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; /* Wait for FIFO empty SPISR_TXBE */ diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c index 449d234343..4431ee6954 100644 --- a/chip/mec1322/system.c +++ b/chip/mec1322/system.c @@ -88,7 +88,7 @@ void system_pre_init(void) MEC1322_EC_TRACE_EN &= ~1; /* Deassert nSIO_RESET */ - MEC1322_PCR_PWR_RST_CTL &= ~(1 << 0); + MEC1322_PCR_PWR_RST_CTL &= ~BIT(0); spi_enable(CONFIG_SPI_FLASH_PORT, 1); } @@ -323,8 +323,8 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds) } if (seconds || microseconds) { - MEC1322_INT_BLK_EN |= 1 << 17; - MEC1322_INT_ENABLE(17) |= 1 << 20; + MEC1322_INT_BLK_EN |= BIT(17); + MEC1322_INT_ENABLE(17) |= BIT(20); interrupt_enable(); task_enable_irq(MEC1322_IRQ_HTIMER); if (seconds > 2) { diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c index ddbe113c7d..af4ccc5b46 100644 --- a/chip/mec1322/uart.c +++ b/chip/mec1322/uart.c @@ -29,7 +29,7 @@ int uart_init_done(void) void uart_tx_start(void) { /* If interrupt is already enabled, nothing to do */ - if (MEC1322_UART_IER & (1 << 1)) + if (MEC1322_UART_IER & BIT(1)) return; /* Do not allow deep sleep while transmit in progress */ @@ -41,13 +41,13 @@ void uart_tx_start(void) * UART where the FIFO only triggers the interrupt when its * threshold is _crossed_, not just met. */ - MEC1322_UART_IER |= (1 << 1); + MEC1322_UART_IER |= BIT(1); task_trigger_irq(MEC1322_IRQ_UART); } void uart_tx_stop(void) { - MEC1322_UART_IER &= ~(1 << 1); + MEC1322_UART_IER &= ~BIT(1); /* Re-allow deep sleep */ enable_sleep(SLEEP_MASK_UART); @@ -77,7 +77,7 @@ int uart_tx_in_progress(void) int uart_rx_available(void) { - return MEC1322_UART_LSR & (1 << 0); + return MEC1322_UART_LSR & BIT(0); } void uart_write_char(char c) @@ -97,7 +97,7 @@ int uart_read_char(void) static void uart_clear_rx_fifo(int channel) { - MEC1322_UART_FCR = (1 << 0) | (1 << 1); + MEC1322_UART_FCR = BIT(0) | BIT(1); } /** @@ -114,31 +114,31 @@ DECLARE_IRQ(MEC1322_IRQ_UART, uart_ec_interrupt, 1); void uart_init(void) { /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MEC1322_UART_CFG &= ~(1 << 1); + MEC1322_UART_CFG &= ~BIT(1); /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ /* Set CLK_SRC = 0 */ - MEC1322_UART_CFG &= ~(1 << 0); + MEC1322_UART_CFG &= ~BIT(0); /* Set DLAB = 1 */ - MEC1322_UART_LCR |= (1 << 7); + MEC1322_UART_LCR |= BIT(7); /* PBRG0/PBRG1 */ MEC1322_UART_PBRG0 = 1; MEC1322_UART_PBRG1 = 0; /* Set DLAB = 0 */ - MEC1322_UART_LCR &= ~(1 << 7); + MEC1322_UART_LCR &= ~BIT(7); /* Set word length to 8-bit */ - MEC1322_UART_LCR |= (1 << 0) | (1 << 1); + MEC1322_UART_LCR |= BIT(0) | BIT(1); /* Enable FIFO */ - MEC1322_UART_FCR = (1 << 0); + MEC1322_UART_FCR = BIT(0); /* Activate UART */ - MEC1322_UART_ACT |= (1 << 0); + MEC1322_UART_ACT |= BIT(0); /* clock_enable_peripheral(CGC_OFFSET_UART, mask, @@ -150,10 +150,10 @@ void uart_init(void) * Enable interrupts for UART0. */ uart_clear_rx_fifo(0); - MEC1322_UART_IER |= (1 << 0); - MEC1322_UART_MCR |= (1 << 3); - MEC1322_INT_ENABLE(15) |= (1 << 0); - MEC1322_INT_BLK_EN |= (1 << 15); + MEC1322_UART_IER |= BIT(0); + MEC1322_UART_MCR |= BIT(3); + MEC1322_INT_ENABLE(15) |= BIT(0); + MEC1322_INT_BLK_EN |= BIT(15); task_enable_irq(MEC1322_IRQ_UART); init_done = 1; @@ -172,7 +172,7 @@ void uart_enter_dsleep(void) gpio_reset(GPIO_UART0_RX); /* power-down/de-activate UART0 */ - MEC1322_UART_ACT &= ~(1 << 0); + MEC1322_UART_ACT &= ~BIT(0); /* Clear pending interrupts on GPIO_UART0_RX(GPIO162, girq=8, bit=18) */ MEC1322_INT_SOURCE(8) = (1<<18); @@ -191,7 +191,7 @@ void uart_exit_dsleep(void) * Note: we can't disable this interrupt if it has already fired * because then the IRQ will not run at all. */ - if (!((1 << 18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */ + if (!(BIT(18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */ gpio_disable_interrupt(GPIO_UART0_RX); /* Configure UART0 pins for use in UART peripheral. */ @@ -202,7 +202,7 @@ void uart_exit_dsleep(void) task_enable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART = 13 */ /* power-up/activate UART0 */ - MEC1322_UART_ACT |= (1 << 0); + MEC1322_UART_ACT |= BIT(0); } void uart_deepsleep_interrupt(enum gpio_signal signal) diff --git a/chip/mec1322/watchdog.c b/chip/mec1322/watchdog.c index a92b57f8a2..07724ca5ee 100644 --- a/chip/mec1322/watchdog.c +++ b/chip/mec1322/watchdog.c @@ -16,9 +16,9 @@ void watchdog_reload(void) #ifdef CONFIG_WATCHDOG_HELP /* Reload the auxiliary timer */ - MEC1322_TMR16_CTL(0) &= ~(1 << 5); + MEC1322_TMR16_CTL(0) &= ~BIT(5); MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MEC1322_TMR16_CTL(0) |= 1 << 5; + MEC1322_TMR16_CTL(0) |= BIT(5); #endif } DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); @@ -34,10 +34,10 @@ int watchdog_init(void) */ /* Stop the auxiliary timer if it's running */ - MEC1322_TMR16_CTL(0) &= ~(1 << 5); + MEC1322_TMR16_CTL(0) &= ~BIT(5); /* Enable auxiliary timer */ - MEC1322_TMR16_CTL(0) |= 1 << 0; + MEC1322_TMR16_CTL(0) |= BIT(0); val = MEC1322_TMR16_CTL(0); @@ -45,22 +45,22 @@ int watchdog_init(void) val = (val & 0xffff) | (47999 << 16); /* No auto restart */ - val &= ~(1 << 3); + val &= ~BIT(3); /* Count down */ - val &= ~(1 << 2); + val &= ~BIT(2); MEC1322_TMR16_CTL(0) = val; /* Enable interrupt from auxiliary timer */ MEC1322_TMR16_IEN(0) |= 1; task_enable_irq(MEC1322_IRQ_TIMER16_0); - MEC1322_INT_ENABLE(23) |= 1 << 0; - MEC1322_INT_BLK_EN |= 1 << 23; + MEC1322_INT_ENABLE(23) |= BIT(0); + MEC1322_INT_BLK_EN |= BIT(23); /* Load and start the auxiliary timer */ MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MEC1322_TMR16_CNT(0) |= 1 << 5; + MEC1322_TMR16_CNT(0) |= BIT(5); #endif /* Set timeout. It takes 1007us to decrement WDG_CNT by 1. */ diff --git a/chip/mt_scp/ipi.c b/chip/mt_scp/ipi.c index 20ce6d4586..d41b39f4d4 100644 --- a/chip/mt_scp/ipi.c +++ b/chip/mt_scp/ipi.c @@ -248,7 +248,7 @@ static int ipi_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions |= (1 << 3); + r->protocol_versions |= BIT(3); r->max_request_packet_size = IPI_MAX_REQUEST_SIZE; r->max_response_packet_size = IPI_MAX_RESPONSE_SIZE; diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h index 2045f8ff30..07634562a9 100644 --- a/chip/mt_scp/registers.h +++ b/chip/mt_scp/registers.h @@ -76,8 +76,8 @@ /* SCP to SPM interrupt */ #define SCP_SPM_INT REG32(SCP_CFG_BASE + 0x20) -#define SPM_INT_A2SPM (1 << 0) -#define SPM_INT_B2SPM (1 << 1) +#define SPM_INT_A2SPM BIT(0) +#define SPM_INT_B2SPM BIT(1) #define SCP_SPM_INT2 REG32(SCP_CFG_BASE + 0x24) /* @@ -101,8 +101,8 @@ */ #define SCP_PWRON_STATE SCP_GPR[1] #define PWRON_DEFAULT 0xdee80000 -#define PWRON_WATCHDOG (1 << 0) -#define PWRON_RESET (1 << 1) +#define PWRON_WATCHDOG BIT(0) +#define PWRON_RESET BIT(1) /* AP defined features */ #define SCP_EXPECTED_FREQ SCP_GPR[3] #define SCP_CURRENT_FREQ SCP_GPR[4] @@ -119,17 +119,17 @@ #define CORE_REG_PSP REG32(SCP_CFG_BASE + 0xB0) #define CORE_REG_PC REG32(SCP_CFG_BASE + 0xB4) #define SCP_SLP_PROTECT_CFG REG32(SCP_CFG_BASE + 0xC8) -#define P_CACHE_SLP_PROT_EN (1 << 3) -#define D_CACHE_SLP_PROT_EN (1 << 4) +#define P_CACHE_SLP_PROT_EN BIT(3) +#define D_CACHE_SLP_PROT_EN BIT(4) #define SCP_ONE_TIME_LOCK REG32(SCP_CFG_BASE + 0xDC) #define SCP_SECURE_CTRL REG32(SCP_CFG_BASE + 0xE0) -#define ENABLE_SPM_MASK_VREQ (1 << 28) -#define DISABLE_REMAP (1 << 22) -#define DISABLE_JTAG (1 << 21) -#define DISABLE_AP_TCM (1 << 20) +#define ENABLE_SPM_MASK_VREQ BIT(28) +#define DISABLE_REMAP BIT(22) +#define DISABLE_JTAG BIT(21) +#define DISABLE_AP_TCM BIT(20) #define SCP_SYS_CTRL REG32(SCP_CFG_BASE + 0xE4) -#define DDREN_FIX_VALUE (1 << 28) -#define AUTO_DDREN (1 << 18) +#define DDREN_FIX_VALUE BIT(28) +#define AUTO_DDREN BIT(18) /* Memory remap control */ /* @@ -191,7 +191,7 @@ #define SCP_INTC_BASE (SCP_CFG_BASE + 0x2000) #define SCP_INTC_IRQ_STATUS REG32(SCP_INTC_BASE) #define SCP_INTC_IRQ_ENABLE REG32(SCP_INTC_BASE + 0x04) -#define IPC0_IRQ_EN (1 << 0) +#define IPC0_IRQ_EN BIT(0) #define SCP_INTC_IRQ_OUTPUT REG32(SCP_INTC_BASE + 0x08) #define SCP_INTC_IRQ_WAKEUP REG32(SCP_INTC_BASE + 0x0C) #define SCP_INTC_NMI REG32(SCP_INTC_BASE + 0x10) @@ -210,12 +210,12 @@ #define SCP_TIMER_RESET_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x04) #define SCP_TIMER_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x08) #define SCP_TIMER_IRQ_CTRL(n) REG32(SCP_TIMER_BASE(n) + 0x0C) -#define TIMER_IRQ_ENABLE (1 << 0) -#define TIMER_IRQ_STATUS (1 << 4) -#define TIMER_IRQ_CLEAR (1 << 5) +#define TIMER_IRQ_ENABLE BIT(0) +#define TIMER_IRQ_STATUS BIT(4) +#define TIMER_IRQ_CLEAR BIT(5) #define SCP_TIMER_CLK_SEL(n) REG32(SCP_TIMER_BASE(n) + 0x40) #define TIMER_CLK_32K (0 << 4) -#define TIMER_CLK_26M (1 << 4) +#define TIMER_CLK_26M BIT(4) #define TIMER_CLK_BCLK (2 << 4) #define TIMER_CLK_PCLK (3 << 4) #define TIMER_CLK_MASK (3 << 4) @@ -228,9 +228,9 @@ #define SCP_OSTIMER_VAL_H REG32(SCP_OSTIMER_BASE + 0x10) #define SCP_OSTIMER_TVAL REG32(SCP_OSTIMER_BASE + 0x14) #define SCP_OSTIMER_IRQ_ACK REG32(SCP_OSTIMER_BASE + 0x18) -#define OSTIMER_LATCH0_EN (1 << 5) -#define OSTIMER_LATCH1_EN (1 << 13) -#define OSTIMER_LATCH2_EN (1 << 21) +#define OSTIMER_LATCH0_EN BIT(5) +#define OSTIMER_LATCH1_EN BIT(13) +#define OSTIMER_LATCH2_EN BIT(21) #define SCP_OSTIMER_LATCH_CTRL REG32(SCP_OSTIMER_BASE + 0x20) #define SCP_OSTIMER_LATCH0_L REG32(SCP_OSTIMER_BASE + 0x24) #define SCP_OSTIMER_LATCH0_H REG32(SCP_OSTIMER_BASE + 0x28) @@ -248,11 +248,11 @@ #define CLK_SEL_ULPOSC_2 3 #define SCP_CLK_EN REG32(SCP_CLK_BASE + 0x04) -#define EN_CLK_SYS (1 << 0) /* System clock */ -#define EN_CLK_HIGH (1 << 1) /* ULPOSC */ -#define CG_CLK_HIGH (1 << 2) -#define EN_SYS_IRQ (1 << 16) -#define EN_HIGH_IRQ (1 << 17) +#define EN_CLK_SYS BIT(0) /* System clock */ +#define EN_CLK_HIGH BIT(1) /* ULPOSC */ +#define CG_CLK_HIGH BIT(2) +#define EN_SYS_IRQ BIT(16) +#define EN_HIGH_IRQ BIT(17) #define SCP_CLK_SAFE_ACK REG32(SCP_CLK_BASE + 0x08) #define SCP_CLK_ACK REG32(SCP_CLK_BASE + 0x0C) #define SCP_CLK_IRQ_ACK REG32(SCP_CLK_BASE + 0x10) @@ -283,43 +283,43 @@ * voltage after returning from sleep mode. */ #define SCP_CLK_SLEEP_CTRL REG32(SCP_CLK_BASE + 0x20) -#define EN_SLEEP_CTRL (1 << 0) +#define EN_SLEEP_CTRL BIT(0) #define VREQ_COUNTER_MASK 0xfe #define VREQ_COUNTER_VAL(v) (((v) << 1) & VREQ_COUNTER_MASK) -#define SPM_SLEEP_MODE (1 << 8) -#define SPM_SLEEP_MODE_CLK_AO (1 << 9) +#define SPM_SLEEP_MODE BIT(8) +#define SPM_SLEEP_MODE_CLK_AO BIT(9) #define SCP_CLK_DIV_SEL REG32(SCP_CLK_BASE + 0x24) #define SCP_CLK_DEBUG REG32(SCP_CLK_BASE + 0x28) #define SCP_CLK_SRAM_POWERDOWN REG32(SCP_CLK_BASE + 0x2C) #define SCP_CLK_GATE REG32(SCP_CLK_BASE + 0x30) -#define CG_TIMER_M (1 << 0) -#define CG_TIMER_B (1 << 1) -#define CG_MAD_M (1 << 2) -#define CG_I2C_M (1 << 3) -#define CG_I2C_B (1 << 4) -#define CG_GPIO_M (1 << 5) -#define CG_AP2P_M (1 << 6) -#define CG_UART_M (1 << 7) -#define CG_UART_B (1 << 8) -#define CG_UART_RSTN (1 << 9) -#define CG_UART1_M (1 << 10) -#define CG_UART1_B (1 << 11) -#define CG_UART1_RSTN (1 << 12) -#define CG_SPI0 (1 << 13) -#define CG_SPI1 (1 << 14) -#define CG_SPI2 (1 << 15) -#define CG_DMA_CH0 (1 << 16) -#define CG_DMA_CH1 (1 << 17) -#define CG_DMA_CH2 (1 << 18) -#define CG_DMA_CH3 (1 << 19) -#define CG_TWAM (1 << 20) -#define CG_CACHE_I_CTRL (1 << 21) -#define CG_CACHE_D_CTRL (1 << 22) +#define CG_TIMER_M BIT(0) +#define CG_TIMER_B BIT(1) +#define CG_MAD_M BIT(2) +#define CG_I2C_M BIT(3) +#define CG_I2C_B BIT(4) +#define CG_GPIO_M BIT(5) +#define CG_AP2P_M BIT(6) +#define CG_UART_M BIT(7) +#define CG_UART_B BIT(8) +#define CG_UART_RSTN BIT(9) +#define CG_UART1_M BIT(10) +#define CG_UART1_B BIT(11) +#define CG_UART1_RSTN BIT(12) +#define CG_SPI0 BIT(13) +#define CG_SPI1 BIT(14) +#define CG_SPI2 BIT(15) +#define CG_DMA_CH0 BIT(16) +#define CG_DMA_CH1 BIT(17) +#define CG_DMA_CH2 BIT(18) +#define CG_DMA_CH3 BIT(19) +#define CG_TWAM BIT(20) +#define CG_CACHE_I_CTRL BIT(21) +#define CG_CACHE_D_CTRL BIT(22) #define SCP_PMICW_CTRL REG32(SCP_CLK_BASE + 0x34) -#define PMICW_SLEEP_REQ (1 << 0) -#define PMICW_SLEEP_ACK (1 << 4) -#define PMICW_CLK_MUX (1 << 8) -#define PMICW_DCM (1 << 9) +#define PMICW_SLEEP_REQ BIT(0) +#define PMICW_SLEEP_ACK BIT(4) +#define PMICW_CLK_MUX BIT(8) +#define PMICW_DCM BIT(9) #define SCP_SLEEP_WAKE_DEBUG REG32(SCP_CLK_BASE + 0x38) #define SCP_DCM_EN REG32(SCP_CLK_BASE + 0x3C) #define SCP_WAKE_CKSW REG32(SCP_CLK_BASE + 0x40) @@ -337,11 +337,11 @@ #define CLK_HIGH_CORE_CG (1 << 1) #define SCP_SLEEP_IRQ2 REG32(SCP_CLK_BASE + 0x64) #define SCP_CLK_ON_CTRL REG32(SCP_CLK_BASE + 0x6C) -#define HIGH_AO (1 << 0) -#define HIGH_CG_AO (1 << 2) -#define HIGH_CORE_AO (1 << 4) -#define HIGH_CORE_DIS_SUB (1 << 5) -#define HIGH_CORE_CG_AO (1 << 6) +#define HIGH_AO BIT(0) +#define HIGH_CG_AO BIT(2) +#define HIGH_CORE_AO BIT(4) +#define HIGH_CORE_DIS_SUB BIT(5) +#define HIGH_CORE_CG_AO BIT(6) #define HIGH_FINAL_VAL_MASK 0x1f00 #define HIGH_FINAL_VAL_DEFAULT 0x300 #define SCP_CLK_L1_SRAM_PD REG32(SCP_CLK_BASE + 0x80) @@ -402,9 +402,9 @@ #define SCP_CACHE_BASE (SCP_CFG_BASE + 0x14000) #define SCP_CACHE_SEL(x) (SCP_CACHE_BASE + (x)*0x3000) #define SCP_CACHE_CON(x) REG32(SCP_CACHE_SEL(x)) -#define SCP_CACHE_CON_MCEN (1 << 0) -#define SCP_CACHE_CON_CNTEN0 (1 << 2) -#define SCP_CACHE_CON_CNTEN1 (1 << 3) +#define SCP_CACHE_CON_MCEN BIT(0) +#define SCP_CACHE_CON_CNTEN0 BIT(2) +#define SCP_CACHE_CON_CNTEN1 BIT(3) #define SCP_CACHE_CON_CACHESIZE_SHIFT 8 #define SCP_CACHE_CON_CACHESIZE_MASK (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) #define SCP_CACHE_CON_CACHESIZE_0KB (0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT) @@ -413,7 +413,7 @@ #define SCP_CACHE_CON_CACHESIZE_32KB (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) #define SCP_CACHE_OP(x) REG32(SCP_CACHE_SEL(x) + 0x04) -#define SCP_CACHE_OP_EN (1 << 0) +#define SCP_CACHE_OP_EN BIT(0) #define SCP_CACHE_OP_OP_SHIFT 1 #define SCP_CACHE_OP_OP_MASK (0xf << SCP_CACHE_OP_OP_SHIFT) @@ -445,12 +445,12 @@ #define SCP_CACHE_END_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2040) #define SCP_CACHE_END_ENTRY(x, reg) REG32(SCP_CACHE_END_ENTRY_BASE(x) + \ (reg)*4) -#define SCP_CACHE_ENTRY_C (1 << 8) +#define SCP_CACHE_ENTRY_C BIT(8) #define SCP_CACHE_ENTRY_BASEADDR_MASK (0xfffff << 12) /* ARMV7 regs */ #define ARM_SCB_SCR REG32(0xE000ED10) -#define SCR_DEEPSLEEP (1 << 2) +#define SCR_DEEPSLEEP BIT(2) /* AP regs */ #define AP_BASE 0xA0000000 @@ -530,11 +530,11 @@ #define OSC_IBAND_MASK (0x7f << 6) #define OSC_FBAND_MASK (0x0f << 13) #define OSC_DIV_MASK (0x1f << 17) -#define OSC_CP_EN (1 << 23) +#define OSC_CP_EN BIT(23) #define OSC_RESERVED_MASK (0xff << 24) /* AP_ULPOSC_CON[1,3] */ #define OSC_MOD_MASK (0x03 << 0) -#define OSC_DIV2_EN (1 << 2) +#define OSC_DIV2_EN BIT(2) #define DUMMY_GPIO_BANK 0 @@ -556,7 +556,7 @@ #define SCP_WDT_FREQ 33825 #define SCP_WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ #define SCP_WDT_PERIOD(ms) (SCP_WDT_FREQ * (ms) / 1000) -#define SCP_WDT_ENABLE (1 << 31) +#define SCP_WDT_ENABLE BIT(31) #define SCP_WDT_RELOAD SCP_WDT_REG(4) #define SCP_WDT_RELOAD_VALUE 1 diff --git a/chip/mt_scp/serial_reg.h b/chip/mt_scp/serial_reg.h index a23b19ded3..5344566272 100644 --- a/chip/mt_scp/serial_reg.h +++ b/chip/mt_scp/serial_reg.h @@ -22,13 +22,13 @@ #define UART_DATA(n) UART_REG(n, 0) /* (Write) Interrupt enable register */ #define UART_IER(n) UART_REG(n, 1) -#define UART_IER_RDI (1 << 0) /* Recv data int */ -#define UART_IER_THRI (1 << 1) /* Xmit holding register int */ -#define UART_IER_RLSI (1 << 2) /* Rcvr line status int */ -#define UART_IER_MSI (1 << 3) /* Modem status int */ +#define UART_IER_RDI BIT(0) /* Recv data int */ +#define UART_IER_THRI BIT(1) /* Xmit holding register int */ +#define UART_IER_RLSI BIT(2) /* Rcvr line status int */ +#define UART_IER_MSI BIT(3) /* Modem status int */ /* (Read) Interrupt ID register */ #define UART_IIR(n) UART_REG(n, 2) -#define UART_IIR_NO_INT (1 << 0) /* No int pending */ +#define UART_IIR_NO_INT BIT(0) /* No int pending */ #define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */ #define UART_IIR_MSI 0x00 #define UART_IIR_THRI 0x02 @@ -37,10 +37,10 @@ #define UART_IIR_BUSY 0x07 /* DW APB busy */ /* (Write) FIFO control register */ #define UART_FCR(n) UART_REG(n, 2) -#define UART_FCR_ENABLE_FIFO (1 << 0) /* Enable FIFO */ -#define UART_FCR_CLEAR_RCVR (1 << 1) /* Clear rcvr FIFO */ -#define UART_FCR_CLEAR_XMIT (1 << 2) /* Clear xmit FIFO */ -#define UART_FCR_DMA_SELECT (1 << 3) +#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */ +#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */ +#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */ +#define UART_FCR_DMA_SELECT BIT(3) /* FIFO trigger levels */ #define UART_FCR_T_TRIG_00 0x00 #define UART_FCR_T_TRIG_01 0x10 @@ -56,24 +56,24 @@ #define UART_LCR_WLEN6 1 #define UART_LCR_WLEN7 2 #define UART_LCR_WLEN8 3 -#define UART_LCR_STOP (1 << 2) /* Stop bits: 1bit, 2bits */ -#define UART_LCR_PARITY (1 << 3) /* Parity enable */ -#define UART_LCR_EPAR (1 << 4) /* Even parity */ -#define UART_LCR_SPAR (1 << 5) /* Stick parity */ -#define UART_LCR_SBC (1 << 6) /* Set break control */ -#define UART_LCR_DLAB (1 << 7) /* Divisor latch access */ +#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */ +#define UART_LCR_PARITY BIT(3) /* Parity enable */ +#define UART_LCR_EPAR BIT(4) /* Even parity */ +#define UART_LCR_SPAR BIT(5) /* Stick parity */ +#define UART_LCR_SBC BIT(6) /* Set break control */ +#define UART_LCR_DLAB BIT(7) /* Divisor latch access */ /* (Write) Modem control register */ #define UART_MCR(n) UART_REG(n, 4) /* (Read) Line status register */ #define UART_LSR(n) UART_REG(n, 5) -#define UART_LSR_DR (1 << 0) /* Data ready */ -#define UART_LSR_OE (1 << 1) /* Overrun error */ -#define UART_LSR_PE (1 << 2) /* Parity error */ -#define UART_LSR_FE (1 << 3) /* Frame error */ -#define UART_LSR_BI (1 << 4) /* Break interrupt */ -#define UART_LSR_THRE (1 << 5) /* Xmit-hold-register empty */ -#define UART_LSR_TEMT (1 << 6) /* Xmit empty */ -#define UART_LSR_FIFOE (1 << 7) /* FIFO error */ +#define UART_LSR_DR BIT(0) /* Data ready */ +#define UART_LSR_OE BIT(1) /* Overrun error */ +#define UART_LSR_PE BIT(2) /* Parity error */ +#define UART_LSR_FE BIT(3) /* Frame error */ +#define UART_LSR_BI BIT(4) /* Break interrupt */ +#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */ +#define UART_LSR_TEMT BIT(6) /* Xmit empty */ +#define UART_LSR_FIFOE BIT(7) /* FIFO error */ /* DLAB == 1 */ diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c index ea016805c0..d996695dfc 100644 --- a/chip/npcx/cec.c +++ b/chip/npcx/cec.c @@ -34,7 +34,7 @@ #endif /* Notification from interrupt to CEC task that data has been received */ -#define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM(1 << 0) +#define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM(BIT(0)) /* CEC broadcast address. Also the highest possible CEC address */ #define CEC_BROADCAST_ADDR 15 diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c index ecd48197b2..178f398434 100644 --- a/chip/npcx/clock.c +++ b/chip/npcx/clock.c @@ -160,7 +160,7 @@ void clock_turbo(void) * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1. */ NPCX_HFCGP = 0x01; - NPCX_HFCBCD = (1 << 4); + NPCX_HFCBCD = BIT(4); } void clock_normal(void) diff --git a/chip/npcx/fan.c b/chip/npcx/fan.c index e6280c97db..381be8a018 100644 --- a/chip/npcx/fan.c +++ b/chip/npcx/fan.c @@ -89,7 +89,7 @@ static int rpm_pre[FAN_CH_COUNT]; ((fan_status[ch].mft_freq * 60 / PULSES_ROUND) / MAX((tach), 1)) /* MFT TCNT default count */ -#define TACHO_MAX_CNT ((1 << 16) - 1) +#define TACHO_MAX_CNT (BIT(16) - 1) /* Margin of target rpm */ #define RPM_MARGIN(rpm_target) (((rpm_target) * RPM_DEVIATION) / 100) diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index a86a5879ba..971512ec72 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -1041,7 +1041,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 3db1c79190..7c812e5da2 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -480,14 +480,14 @@ enum { }; enum { - MASK_PIN0 = (1<<0), - MASK_PIN1 = (1<<1), - MASK_PIN2 = (1<<2), - MASK_PIN3 = (1<<3), - MASK_PIN4 = (1<<4), - MASK_PIN5 = (1<<5), - MASK_PIN6 = (1<<6), - MASK_PIN7 = (1<<7), + MASK_PIN0 = BIT(0), + MASK_PIN1 = BIT(1), + MASK_PIN2 = BIT(2), + MASK_PIN3 = BIT(3), + MASK_PIN4 = BIT(4), + MASK_PIN5 = BIT(5), + MASK_PIN6 = BIT(6), + MASK_PIN7 = BIT(7), }; /* Chip-independent aliases for port base group */ @@ -1863,21 +1863,21 @@ enum { /* * Status registers for the W25Q16CV SPI flash */ -#define SPI_FLASH_SR2_SUS (1 << 7) -#define SPI_FLASH_SR2_CMP (1 << 6) -#define SPI_FLASH_SR2_LB3 (1 << 5) -#define SPI_FLASH_SR2_LB2 (1 << 4) -#define SPI_FLASH_SR2_LB1 (1 << 3) -#define SPI_FLASH_SR2_QE (1 << 1) -#define SPI_FLASH_SR2_SRP1 (1 << 0) -#define SPI_FLASH_SR1_SRP0 (1 << 7) -#define SPI_FLASH_SR1_SEC (1 << 6) -#define SPI_FLASH_SR1_TB (1 << 5) -#define SPI_FLASH_SR1_BP2 (1 << 4) -#define SPI_FLASH_SR1_BP1 (1 << 3) -#define SPI_FLASH_SR1_BP0 (1 << 2) -#define SPI_FLASH_SR1_WEL (1 << 1) -#define SPI_FLASH_SR1_BUSY (1 << 0) +#define SPI_FLASH_SR2_SUS BIT(7) +#define SPI_FLASH_SR2_CMP BIT(6) +#define SPI_FLASH_SR2_LB3 BIT(5) +#define SPI_FLASH_SR2_LB2 BIT(4) +#define SPI_FLASH_SR2_LB1 BIT(3) +#define SPI_FLASH_SR2_QE BIT(1) +#define SPI_FLASH_SR2_SRP1 BIT(0) +#define SPI_FLASH_SR1_SRP0 BIT(7) +#define SPI_FLASH_SR1_SEC BIT(6) +#define SPI_FLASH_SR1_TB BIT(5) +#define SPI_FLASH_SR1_BP2 BIT(4) +#define SPI_FLASH_SR1_BP1 BIT(3) +#define SPI_FLASH_SR1_BP0 BIT(2) +#define SPI_FLASH_SR1_WEL BIT(1) +#define SPI_FLASH_SR1_BUSY BIT(0) /* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */ diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c index 464ad9db5f..2e061ad2c2 100644 --- a/chip/npcx/shi.c +++ b/chip/npcx/shi.c @@ -1055,7 +1055,7 @@ static int shi_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = SHI_MAX_REQUEST_SIZE; r->max_response_packet_size = SHI_MAX_RESPONSE_SIZE; r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED; diff --git a/chip/npcx/system.c b/chip/npcx/system.c index 726aa30350..b9d3367d91 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -25,7 +25,7 @@ /* Delay after writing TTC for value to latch */ #define MTC_TTC_LOAD_DELAY_US 250 -#define MTC_ALARM_MASK ((1 << 25) - 1) +#define MTC_ALARM_MASK (BIT(25) - 1) #define MTC_WUI_GROUP MIWU_GROUP_4 #define MTC_WUI_MASK MASK_PIN7 @@ -266,7 +266,7 @@ void system_set_rtc(uint32_t seconds) #define BKUP_LREG3 (BBRM_DATA_INDEX_PANIC_BKUP + 16) #define BKUP_LREG4 (BBRM_DATA_INDEX_PANIC_BKUP + 20) -#define BKUP_PANIC_DATA_VALID (1 << 0) +#define BKUP_PANIC_DATA_VALID BIT(0) void chip_panic_data_backup(void) { diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h index da400f79bb..5700143e2a 100644 --- a/chip/npcx/system_chip.h +++ b/chip/npcx/system_chip.h @@ -9,8 +9,8 @@ #define __CROS_EC_SYSTEM_CHIP_H /* Flags for BBRM_DATA_INDEX_WAKE */ -#define HIBERNATE_WAKE_MTC (1 << 0) /* MTC alarm */ -#define HIBERNATE_WAKE_PIN (1 << 1) /* Wake pin */ +#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */ +#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */ /* Indices for battery-backed ram (BBRAM) data position */ enum bbram_data_index { diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c index 2d0574ff01..3bbeee90a0 100644 --- a/chip/npcx/wov.c +++ b/chip/npcx/wov.c @@ -1743,12 +1743,12 @@ void wov_set_i2s_bclk(uint32_t i2s_clock) * first bit (MSB) of channel 1 (right channel). * If channel 1 is not used set this field to -1. * - * @param flags - WOV_TDM_ADJACENT_TO_CH0 = (1 << 0). There is a + * @param flags - WOV_TDM_ADJACENT_TO_CH0 = BIT(0). There is a * channel adjacent to channel 0, so float SDAT when * driving the last bit (LSB) of the channel during the * second half of the clock cycle to avoid bus contention. * - * WOV_TDM_ADJACENT_TO_CH1 = (1 << 1). There is a channel + * WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel * adjacent to channel 1. * * @return EC error code. diff --git a/chip/npcx/wov_chip.h b/chip/npcx/wov_chip.h index 96bc03c2b8..dce534c501 100644 --- a/chip/npcx/wov_chip.h +++ b/chip/npcx/wov_chip.h @@ -427,12 +427,12 @@ void wov_set_i2s_bclk(uint32_t i2s_clock); * first bit (MSB) of channel 1 (right channel). * If channel 1 is not used set this field to -1. * - * @param flags - WOV_TDM_ADJACENT_TO_CH0 = (1 << 0). There is a + * @param flags - WOV_TDM_ADJACENT_TO_CH0 = BIT(0). There is a * channel adjacent to channel 0, so float SDAT when * driving the last bit (LSB) of the channel during the * second half of the clock cycle to avoid bus contention. * - * WOV_TDM_ADJACENT_TO_CH1 = (1 << 1). There is a channel + * WOV_TDM_ADJACENT_TO_CH1 = BIT(1). There is a channel * adjacent to channel 1. * * @return EC error code. diff --git a/chip/nrf51/radio_test.c b/chip/nrf51/radio_test.c index bcad7466e9..5afb30425b 100644 --- a/chip/nrf51/radio_test.c +++ b/chip/nrf51/radio_test.c @@ -111,7 +111,7 @@ static int ble_test_init(int chan) if (chan > BLE_MAX_TEST_CHANNEL || chan < BLE_MIN_TEST_CHANNEL) return HCI_ERR_Invalid_HCI_Command_Parameters; - NRF51_RADIO_CRCCNF = 3 | (1 << 8); /* 3-byte, skip address */ + NRF51_RADIO_CRCCNF = 3 | BIT(8); /* 3-byte, skip address */ /* x^24 + x^10 + x^9 + x^6 + x^4 + x^3 + x + 1 */ /* 0x1_0000_0000_0000_0110_0101_1011 */ NRF51_RADIO_CRCPOLY = 0x100065B; diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h index e9d2003f33..c92c66dde9 100644 --- a/chip/nrf51/registers.h +++ b/chip/nrf51/registers.h @@ -361,7 +361,7 @@ #define NRF51_RADIO_TXADD_MAX 8 /* OVERRIDE4 */ -#define NRF51_RADIO_OVERRIDE_EN (1 << 31) +#define NRF51_RADIO_OVERRIDE_EN BIT(31) /* @@ -433,8 +433,8 @@ #define NRF51_TWI_ENABLE_VAL 0x5 #define NRF51_TWI_DISABLE_VAL 0x0 -#define NRF51_TWI_ERRORSRC_ANACK (1<<1) /* Address NACK */ -#define NRF51_TWI_ERRORSRC_DNACK (1<<2) /* Data NACK */ +#define NRF51_TWI_ERRORSRC_ANACK BIT(1) /* Address NACK */ +#define NRF51_TWI_ERRORSRC_DNACK BIT(2) /* Data NACK */ /* * TWI (I2C) Instance 0 @@ -526,14 +526,14 @@ #define NRF51_GPIOTE_PORT_BIT 31 /* For GPIOTE.CONFIG */ #define NRF51_GPIOTE_MODE_DISABLED (0<<0) -#define NRF51_GPIOTE_MODE_EVENT (1<<0) +#define NRF51_GPIOTE_MODE_EVENT BIT(0) #define NRF51_GPIOTE_MODE_TASK (3<<0) #define NRF51_GPIOTE_PSEL_POS (8) -#define NRF51_GPIOTE_POLARITY_LOTOHI (1<<16) +#define NRF51_GPIOTE_POLARITY_LOTOHI BIT(16) #define NRF51_GPIOTE_POLARITY_HITOLO (2<<16) #define NRF51_GPIOTE_POLARITY_TOGGLE (3<<16) #define NRF51_GPIOTE_OUTINIT_LOW (0<<20) -#define NRF51_GPIOTE_OUTINIT_HIGH (1<<20) +#define NRF51_GPIOTE_OUTINIT_HIGH BIT(20) /* * Timer / Counter @@ -590,9 +590,9 @@ #define NRF51_RNG_CONFIG REG32(NRF51_RNG_BASE + 0x504) #define NRF51_RNG_VALUE REG32(NRF51_RNG_BASE + 0x508) /* For RNG Shortcuts */ -#define NRF51_RNG_SHORTS_VALRDY_STOP (1 << 0) +#define NRF51_RNG_SHORTS_VALRDY_STOP BIT(0) /* For RNG Config */ -#define NRF51_RNG_DERCEN (1 << 0) +#define NRF51_RNG_DERCEN BIT(0) /* @@ -620,7 +620,7 @@ #define NRF51_WDT_CONFIG_SLEEP_PAUSE 0 #define NRF51_WDT_CONFIG_SLEEP_RUN 1 #define NRF51_WDT_CONFIG_HALT_PAUSE (0<<4) -#define NRF51_WDT_CONFIG_HALT_RUN (1<<4) +#define NRF51_WDT_CONFIG_HALT_RUN BIT(4) #define NRF51_WDT_RELOAD_VAL 0x6E524635 @@ -644,16 +644,16 @@ #define NRF51_PIN_CNF_DIR_INPUT (0) #define NRF51_PIN_CNF_DIR_OUTPUT (1) #define NRF51_PIN_CNF_INPUT_CONNECT (0<<1) -#define NRF51_PIN_CNF_INPUT_DISCONNECT (1<<1) +#define NRF51_PIN_CNF_INPUT_DISCONNECT BIT(1) #define NRF51_PIN_CNF_PULL_DISABLED (0<<2) -#define NRF51_PIN_CNF_PULLDOWN (1<<2) +#define NRF51_PIN_CNF_PULLDOWN BIT(2) #define NRF51_PIN_CNF_PULLUP (3<<2) /* * Logic levels 0 and 1, strengths S=Standard, H=High D=Disconnect * for example, S0D1 = Standard drive 0, disconnect on 1 */ #define NRF51_PIN_CNF_DRIVE_S0S1 (0<<8) -#define NRF51_PIN_CNF_DRIVE_H0S1 (1<<8) +#define NRF51_PIN_CNF_DRIVE_H0S1 BIT(8) #define NRF51_PIN_CNF_DRIVE_S0H1 (2<<8) #define NRF51_PIN_CNF_DRIVE_H0H1 (3<<8) #define NRF51_PIN_CNF_DRIVE_D0S1 (4<<8) diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c index 0f31e3b286..3836767d1f 100644 --- a/chip/stm32/adc-stm32f0.c +++ b/chip/stm32/adc-stm32f0.c @@ -75,7 +75,7 @@ static void adc_init(void) * If clock is already enabled, and ADC module is enabled * then this is a warm reboot and ADC is already initialized. */ - if (STM32_RCC_APB2ENR & (1 << 9) && (STM32_ADC_CR & STM32_ADC_CR_ADEN)) + if (STM32_RCC_APB2ENR & BIT(9) && (STM32_ADC_CR & STM32_ADC_CR_ADEN)) return; /* Enable ADC clock */ @@ -107,7 +107,7 @@ static void adc_init(void) static void adc_configure(int ain_id) { /* Select channel to convert */ - STM32_ADC_CHSELR = 1 << ain_id; + STM32_ADC_CHSELR = BIT(ain_id); /* Disable DMA */ STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_DMAEN; @@ -126,16 +126,16 @@ static void adc_continuous_read(int ain_id) STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_CONT; /* Start continuous conversion */ - STM32_ADC_CR |= 1 << 2; /* ADSTART */ + STM32_ADC_CR |= BIT(2); /* ADSTART */ } static void adc_continuous_stop(void) { /* Stop on-going conversion */ - STM32_ADC_CR |= 1 << 4; /* ADSTP */ + STM32_ADC_CR |= BIT(4); /* ADSTP */ /* Wait for conversion to stop */ - while (STM32_ADC_CR & (1 << 4)) + while (STM32_ADC_CR & BIT(4)) ; /* CONT=0 -> continuous mode off */ @@ -173,7 +173,7 @@ static void adc_interval_read(int ain_id, int interval_ms) STM32_TIM_CR1(TIM_ADC) |= 1; /* Start ADC conversion */ - STM32_ADC_CR |= 1 << 2; /* ADSTART */ + STM32_ADC_CR |= BIT(2); /* ADSTART */ } static void adc_interval_stop(void) @@ -182,10 +182,10 @@ static void adc_interval_stop(void) STM32_ADC_CFGR1 &= ~STM32_ADC_CFGR1_EXTEN_MASK; /* Set ADSTP to clear ADSTART */ - STM32_ADC_CR |= 1 << 4; /* ADSTP */ + STM32_ADC_CR |= BIT(4); /* ADSTP */ /* Wait for conversion to stop */ - while (STM32_ADC_CR & (1 << 4)) + while (STM32_ADC_CR & BIT(4)) ; /* Stop the timer */ @@ -307,10 +307,10 @@ int adc_read_channel(enum adc_channel ch) STM32_ADC_ISR = 0xe; /* Start conversion */ - STM32_ADC_CR |= 1 << 2; /* ADSTART */ + STM32_ADC_CR |= BIT(2); /* ADSTART */ /* Wait for end of conversion */ - while (!(STM32_ADC_ISR & (1 << 2))) + while (!(STM32_ADC_ISR & BIT(2))) ; /* read converted value */ value = STM32_ADC_DR; diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c index 6e22c49ac3..7bee47c319 100644 --- a/chip/stm32/adc-stm32f3.c +++ b/chip/stm32/adc-stm32f3.c @@ -59,10 +59,10 @@ static void adc_configure(int ain_id) adc_set_channel(0, ain_id); /* Disable DMA */ - STM32_ADC_CR2 &= ~(1 << 8); + STM32_ADC_CR2 &= ~BIT(8); /* Disable scan mode */ - STM32_ADC_CR1 &= ~(1 << 8); + STM32_ADC_CR1 &= ~BIT(8); } static void __attribute__((unused)) adc_configure_all(void) @@ -75,25 +75,25 @@ static void __attribute__((unused)) adc_configure_all(void) adc_set_channel(i, adc_channels[i].channel); /* Enable DMA */ - STM32_ADC_CR2 |= (1 << 8); + STM32_ADC_CR2 |= BIT(8); /* Enable scan mode */ - STM32_ADC_CR1 |= (1 << 8); + STM32_ADC_CR1 |= BIT(8); } static inline int adc_powered(void) { - return STM32_ADC_CR2 & (1 << 0); + return STM32_ADC_CR2 & BIT(0); } static inline int adc_conversion_ended(void) { - return STM32_ADC_SR & (1 << 1); + return STM32_ADC_SR & BIT(1); } static int adc_watchdog_enabled(void) { - return STM32_ADC_CR1 & (1 << 23); + return STM32_ADC_CR1 & BIT(23); } static int adc_enable_watchdog_no_lock(void) @@ -111,16 +111,16 @@ static int adc_enable_watchdog_no_lock(void) STM32_ADC_SR &= ~0x1; /* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */ - STM32_ADC_CR1 |= (1 << 9) | (1 << 8) | (1 << 6) | (1 << 23); + STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23); /* Disable DMA */ - STM32_ADC_CR2 &= ~(1 << 8); + STM32_ADC_CR2 &= ~BIT(8); /* CONT=1 */ - STM32_ADC_CR2 |= (1 << 1); + STM32_ADC_CR2 |= BIT(1); /* Start conversion */ - STM32_ADC_CR2 |= (1 << 0); + STM32_ADC_CR2 |= BIT(0); return EC_SUCCESS; } @@ -152,10 +152,10 @@ static int adc_disable_watchdog_no_lock(void) return EC_ERROR_UNKNOWN; /* AWDEN=0, AWDIE=0 */ - STM32_ADC_CR1 &= ~(1 << 23) & ~(1 << 6); + STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6); /* CONT=0 */ - STM32_ADC_CR2 &= ~(1 << 1); + STM32_ADC_CR2 &= ~BIT(1); return EC_SUCCESS; } @@ -193,7 +193,7 @@ int adc_read_channel(enum adc_channel ch) adc_configure(adc->channel); /* Clear EOC bit */ - STM32_ADC_SR &= ~(1 << 1); + STM32_ADC_SR &= ~BIT(1); /* Start conversion (Note: For now only confirmed on F4) */ #if defined(CHIP_FAMILY_STM32F4) diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c index 270d953252..69cacb0d0e 100644 --- a/chip/stm32/adc-stm32l.c +++ b/chip/stm32/adc-stm32l.c @@ -42,10 +42,10 @@ static void adc_configure(int ain_id) adc_set_channel(0, ain_id); /* Disable DMA */ - STM32_ADC_CR2 &= ~(1 << 8); + STM32_ADC_CR2 &= ~BIT(8); /* Disable scan mode */ - STM32_ADC_CR1 &= ~(1 << 8); + STM32_ADC_CR1 &= ~BIT(8); } static void adc_configure_all(void) @@ -58,22 +58,22 @@ static void adc_configure_all(void) adc_set_channel(i, adc_channels[i].channel); /* Enable DMA */ - STM32_ADC_CR2 |= (1 << 8); + STM32_ADC_CR2 |= BIT(8); /* Enable scan mode */ - STM32_ADC_CR1 |= (1 << 8); + STM32_ADC_CR1 |= BIT(8); } static inline int adc_powered(void) { - return STM32_ADC_SR & (1 << 6); /* ADONS */ + return STM32_ADC_SR & BIT(6); /* ADONS */ } static void adc_enable_clock(void) { - STM32_RCC_APB2ENR |= (1 << 9); + STM32_RCC_APB2ENR |= BIT(9); /* ADCCLK = HSI / 2 = 8MHz*/ - STM32_ADC_CCR |= (1 << 16); + STM32_ADC_CCR |= BIT(16); } static void adc_init(void) @@ -92,10 +92,10 @@ static void adc_init(void) if (!adc_powered()) /* Power on ADC module */ - STM32_ADC_CR2 |= (1 << 0); /* ADON */ + STM32_ADC_CR2 |= BIT(0); /* ADON */ /* Set right alignment */ - STM32_ADC_CR2 &= ~(1 << 11); + STM32_ADC_CR2 &= ~BIT(11); /* * Set sample time of all channels to 16 cycles. @@ -132,7 +132,7 @@ static void adc_release(void) static inline int adc_conversion_ended(void) { - return STM32_ADC_SR & (1 << 1); + return STM32_ADC_SR & BIT(1); } int adc_read_channel(enum adc_channel ch) @@ -148,10 +148,10 @@ int adc_read_channel(enum adc_channel ch) adc_configure(adc->channel); /* Clear EOC bit */ - STM32_ADC_SR &= ~(1 << 1); + STM32_ADC_SR &= ~BIT(1); /* Start conversion */ - STM32_ADC_CR2 |= (1 << 30); /* SWSTART */ + STM32_ADC_CR2 |= BIT(30); /* SWSTART */ /* Wait for EOC bit set */ deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT; diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index 26188d97fd..24da104c3d 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -113,11 +113,11 @@ void config_hispeed_clock(void) { #ifdef CHIP_FAMILY_STM32F3 /* Ensure that HSE is ON */ - if (!(STM32_RCC_CR & (1 << 17))) { + if (!(STM32_RCC_CR & BIT(17))) { /* Enable HSE */ - STM32_RCC_CR |= 1 << 16; + STM32_RCC_CR |= BIT(16); /* Wait for HSE to be ready */ - while (!(STM32_RCC_CR & (1 << 17))) + while (!(STM32_RCC_CR & BIT(17))) ; } @@ -186,11 +186,11 @@ defined(CHIP_VARIANT_STM32F070) ; #else /* Ensure that HSI48 is ON */ - if (!(STM32_RCC_CR2 & (1 << 17))) { + if (!(STM32_RCC_CR2 & BIT(17))) { /* Enable HSI */ - STM32_RCC_CR2 |= 1 << 16; + STM32_RCC_CR2 |= BIT(16); /* Wait for HSI to be ready */ - while (!(STM32_RCC_CR2 & (1 << 17))) + while (!(STM32_RCC_CR2 & BIT(17))) ; } diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c index 95d9b1e96c..30faa0035a 100644 --- a/chip/stm32/clock-stm32h7.c +++ b/chip/stm32/clock-stm32h7.c @@ -249,8 +249,8 @@ static void low_power_init(void) task_enable_irq(STM32_IRQ_LPTIM1); /* Wake-up interrupts from EXTI for USART and LPTIM */ - STM32_EXTI_CPUIMR1 |= 1 << 26; /* [26] wkup26: USART1 wake-up */ - STM32_EXTI_CPUIMR2 |= 1 << 15; /* [15] wkup47: LPTIM1 wake-up */ + STM32_EXTI_CPUIMR1 |= BIT(26); /* [26] wkup26: USART1 wake-up */ + STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */ /* optimize power vs latency in STOP mode */ STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK) diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c index 93706c7019..b0903b5cb1 100644 --- a/chip/stm32/clock-stm32l.c +++ b/chip/stm32/clock-stm32l.c @@ -33,8 +33,8 @@ static int fake_hibernate; * because it's the lowest clock rate we can still run 115200 baud serial * for the debug console. */ -#define MSI_2MHZ_CLOCK (1 << 21) -#define MSI_1MHZ_CLOCK (1 << 20) +#define MSI_2MHZ_CLOCK BIT(21) +#define MSI_1MHZ_CLOCK BIT(20) enum clock_osc { OSC_INIT = 0, /* Uninitialized */ diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h index d6959310d6..038dc76f7c 100644 --- a/chip/stm32/crc_hw.h +++ b/chip/stm32/crc_hw.h @@ -13,7 +13,7 @@ static inline void crc32_init(void) { /* switch on CRC controller */ - STM32_RCC_AHBENR |= 1 << 6; /* switch on CRC controller */ + STM32_RCC_AHBENR |= BIT(6); /* switch on CRC controller */ /* Delay 1 AHB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_AHB, 1); /* reset CRC state */ diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index fcd4b19e12..dd248e62f8 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -414,7 +414,7 @@ void hwtimer_setup_watchdog(void) * Timer configuration : Down counter, counter disabled, update * event only on overflow. */ - timer->cr1 = 0x0014 | (1 << 7); + timer->cr1 = 0x0014 | BIT(7); /* TIM (slave mode) uses TIM_CLOCK_LSB as internal trigger */ timer->smcr = 0x0007 | (TSMAP(TIM_WATCHDOG, TIM_CLOCK_LSB) << 4); @@ -426,7 +426,7 @@ void hwtimer_setup_watchdog(void) * to obtain the number of times TIM_CLOCK_LSB can overflow before we * generate an interrupt. */ - timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / (1 << 16); + timer->arr = timer->cnt = CONFIG_AUX_TIMER_PERIOD_MS * MSEC / BIT(16); /* count on every TIM_CLOCK_LSB overflow */ timer->psc = 0; diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c index ce2f8636f6..45d489a8c0 100644 --- a/chip/stm32/pwm.c +++ b/chip/stm32/pwm.c @@ -69,9 +69,9 @@ static void pwm_configure(enum pwm_channel ch) /* Output, PWM mode 1, preload enable */ if (pwm->channel & 0x1) - *ccmr = (6 << 4) | (1 << 3); + *ccmr = (6 << 4) | BIT(3); else - *ccmr = (6 << 12) | (1 << 11); + *ccmr = (6 << 12) | BIT(11); /* Output enable. Set active high/low. */ if (pwm->flags & PWM_CONFIG_ACTIVE_LOW) @@ -90,13 +90,13 @@ static void pwm_configure(enum pwm_channel ch) * TODO(shawnn): BDTR is undocumented on STM32L. Verify this isn't * harmful on STM32L. */ - tim->bdtr |= (1 << 15); + tim->bdtr |= BIT(15); /* Generate update event to force loading of shadow registers */ tim->egr |= 1; /* Enable auto-reload preload, start counting */ - tim->cr1 |= (1 << 7) | (1 << 0); + tim->cr1 |= BIT(7) | BIT(0); atomic_or(&using_pwm, 1 << ch); @@ -113,7 +113,7 @@ static void pwm_disable(enum pwm_channel ch) return; /* Main output disable */ - tim->bdtr &= ~(1 << 15); + tim->bdtr &= ~BIT(15); /* Disable counter */ tim->cr1 &= ~0x1; diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c index de10176c77..eda4e0960f 100644 --- a/chip/stm32/spi.c +++ b/chip/stm32/spi.c @@ -715,9 +715,9 @@ static int spi_get_protocol_info(struct host_cmd_handler_args *args) memset(r, 0, sizeof(*r)); #ifdef CONFIG_SPI_PROTOCOL_V2 - r->protocol_versions |= (1 << 2); + r->protocol_versions |= BIT(2); #endif - r->protocol_versions |= (1 << 3); + r->protocol_versions |= BIT(3); r->max_request_packet_size = SPI_MAX_REQUEST_SIZE; r->max_response_packet_size = SPI_MAX_RESPONSE_SIZE; r->flags = EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED; diff --git a/chip/stm32/system.c b/chip/stm32/system.c index c7ff4f23d9..5f6124657e 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -285,24 +285,24 @@ void system_pre_init(void) STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_BKPSRAMEN; #elif defined(CHIP_FAMILY_STM32H7) /* enable backup registers */ - STM32_RCC_AHB4ENR |= 1 << 28; + STM32_RCC_AHB4ENR |= BIT(28); #else /* enable backup registers */ - STM32_RCC_APB1ENR |= 1 << 27; + STM32_RCC_APB1ENR |= BIT(27); #endif /* Delay 1 APB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_APB, 1); /* Enable access to RCC CSR register and RTC backup registers */ - STM32_PWR_CR |= 1 << 8; + STM32_PWR_CR |= BIT(8); #ifdef CHIP_VARIANT_STM32L476 /* Enable Vddio2 */ - STM32_PWR_CR2 |= 1 << 9; + STM32_PWR_CR2 |= BIT(9); #endif /* switch on LSI */ - STM32_RCC_CSR |= 1 << 0; + STM32_RCC_CSR |= BIT(0); /* Wait for LSI to be ready */ - while (!(STM32_RCC_CSR & (1 << 1))) + while (!(STM32_RCC_CSR & BIT(1))) ; /* re-configure RTC if needed */ #ifdef CHIP_FAMILY_STM32L diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c index 0ef357466c..4d3ea20b8c 100644 --- a/chip/stm32/usart.c +++ b/chip/stm32/usart.c @@ -47,12 +47,12 @@ void usart_init(struct usart_config const *config) #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ defined(CHIP_FAMILY_STM32L4) if (config->flags & USART_CONFIG_FLAG_RX_INV) - cr2 |= (1 << 16); + cr2 |= BIT(16); if (config->flags & USART_CONFIG_FLAG_TX_INV) - cr2 |= (1 << 17); + cr2 |= BIT(17); #endif if (config->flags & USART_CONFIG_FLAG_HDSEL) - cr3 |= (1 << 3); + cr3 |= BIT(3); STM32_USART_CR1(base) = 0x0000; STM32_USART_CR2(base) = cr2; diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h index 53b13762e9..771c0ccfde 100644 --- a/chip/stm32/usart.h +++ b/chip/stm32/usart.h @@ -134,9 +134,9 @@ struct usart_config { int baud; /* Other flags (rx/tx inversion, half-duplex). */ -#define USART_CONFIG_FLAG_RX_INV (1 << 0) -#define USART_CONFIG_FLAG_TX_INV (1 << 1) -#define USART_CONFIG_FLAG_HDSEL (1 << 2) +#define USART_CONFIG_FLAG_RX_INV BIT(0) +#define USART_CONFIG_FLAG_TX_INV BIT(1) +#define USART_CONFIG_FLAG_HDSEL BIT(2) unsigned int flags; struct consumer consumer; diff --git a/chip/stm32/usb-stm32f0.c b/chip/stm32/usb-stm32f0.c index 97bb93cafd..de755f2fdd 100644 --- a/chip/stm32/usb-stm32f0.c +++ b/chip/stm32/usb-stm32f0.c @@ -14,13 +14,13 @@ void usb_connect(void) /* USB is in use */ disable_sleep(SLEEP_MASK_USB_DEVICE); - STM32_USB_BCDR |= (1 << 15) /* DPPU */; + STM32_USB_BCDR |= BIT(15) /* DPPU */; } void usb_disconnect(void) { /* disable pull-up on DP to disconnect */ - STM32_USB_BCDR &= ~(1 << 15) /* DPPU */; + STM32_USB_BCDR &= ~BIT(15) /* DPPU */; /* USB is off, so sleep whenever */ enable_sleep(SLEEP_MASK_USB_DEVICE); diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c index c8768823d7..82b418707a 100644 --- a/chip/stm32/usb.c +++ b/chip/stm32/usb.c @@ -351,7 +351,7 @@ static void ep0_event(enum usb_ep_event evt) if (evt != USB_EVENT_RESET) return; - STM32_USB_EP(0) = (1 << 9) /* control EP */ | + STM32_USB_EP(0) = BIT(9) /* control EP */ | (2 << 4) /* TX NAK */ | (3 << 12) /* RX VALID */; @@ -673,8 +673,8 @@ void usb_init(void) STM32_USB_BTABLE = 0; /* EXTI18 is USB wake up interrupt */ - /* STM32_EXTI_RTSR |= 1 << 18; */ - /* STM32_EXTI_IMR |= 1 << 18; */ + /* STM32_EXTI_RTSR |= BIT(18); */ + /* STM32_EXTI_IMR |= BIT(18); */ /* Enable interrupt handlers */ task_enable_irq(STM32_IRQ_USB_LP); diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h index 9d656df22d..f8b90c1d1f 100644 --- a/chip/stm32/usb_dwc_registers.h +++ b/chip/stm32/usb_dwc_registers.h @@ -131,8 +131,8 @@ extern struct dwc_usb usb_ctl; #define GR_USB_GNPTXFSIZ GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET) /*#define GR_USB_GGPIO GR_USB_REG(GC_USB_GGPIO_OFFSET)*/ #define GR_USB_GCCFG GR_USB_REG(GC_USB_GCCFG_OFFSET) -#define GCCFG_VBDEN (1 << 21) -#define GCCFG_PWRDWN (1 << 16) +#define GCCFG_VBDEN BIT(21) +#define GCCFG_PWRDWN BIT(16) #define GR_USB_PCGCCTL GR_USB_REG(GC_USB_PCGCCTL_OFFSET) #define GR_USB_GSNPSID GR_USB_REG(GC_USB_GSNPSID_OFFSET) @@ -156,9 +156,9 @@ extern struct dwc_usb usb_ctl; #define GR_USB_DTHRCTL GR_USB_REG(GC_USB_DTHRCTL_OFFSET) #define DTHRCTL_TXTHRLEN_6 (0x40 << 2) #define DTHRCTL_RXTHRLEN_6 (0x40 << 17) -#define DTHRCTL_RXTHREN (1 << 16) -#define DTHRCTL_ISOTHREN (1 << 1) -#define DTHRCTL_NONISOTHREN (1 << 0) +#define DTHRCTL_RXTHREN BIT(16) +#define DTHRCTL_ISOTHREN BIT(1) +#define DTHRCTL_NONISOTHREN BIT(0) #define GR_USB_DIEPEMPMSK GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET) #define GR_USB_EPIREG(off, n) GR_USB_REG(0x900 + (n) * 0x20 + (off)) @@ -176,7 +176,7 @@ extern struct dwc_usb usb_ctl; #define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n) #define GOTGCTL_BVALOEN (1 << GC_USB_GOTGCTL_BVALIDOVEN_LSB) -#define GOTGCTL_BVALOVAL (1 << 7) +#define GOTGCTL_BVALOVAL BIT(7) /* Bit 5 */ #define GAHBCFG_DMA_EN (1 << GC_USB_GAHBCFG_DMAEN_LSB) @@ -187,7 +187,7 @@ extern struct dwc_usb usb_ctl; /* Bit 7 */ #define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB) #define GAHBCFG_TXFELVL GAHBCFG_NP_TXF_EMP_LVL -#define GAHBCFG_PTXFELVL (1 << 8) +#define GAHBCFG_PTXFELVL BIT(8) #define GUSBCFG_TOUTCAL(n) (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \ & GC_USB_GUSBCFG_TOUTCAL_MASK) @@ -195,19 +195,19 @@ extern struct dwc_usb usb_ctl; & GC_USB_GUSBCFG_USBTRDTIM_MASK) /* Force device mode */ #define GUSBCFG_FDMOD (1 << GC_USB_GUSBCFG_FDMOD_LSB) -#define GUSBCFG_PHYSEL (1 << 6) -#define GUSBCFG_SRPCAP (1 << 8) -#define GUSBCFG_HNPCAP (1 << 9) -#define GUSBCFG_ULPIFSLS (1 << 17) -#define GUSBCFG_ULPIAR (1 << 18) -#define GUSBCFG_ULPICSM (1 << 19) -#define GUSBCFG_ULPIEVBUSD (1 << 20) -#define GUSBCFG_ULPIEVBUSI (1 << 21) -#define GUSBCFG_TSDPS (1 << 22) -#define GUSBCFG_PCCI (1 << 23) -#define GUSBCFG_PTCI (1 << 24) -#define GUSBCFG_ULPIIPD (1 << 25) -#define GUSBCFG_TSDPS (1 << 22) +#define GUSBCFG_PHYSEL BIT(6) +#define GUSBCFG_SRPCAP BIT(8) +#define GUSBCFG_HNPCAP BIT(9) +#define GUSBCFG_ULPIFSLS BIT(17) +#define GUSBCFG_ULPIAR BIT(18) +#define GUSBCFG_ULPICSM BIT(19) +#define GUSBCFG_ULPIEVBUSD BIT(20) +#define GUSBCFG_ULPIEVBUSI BIT(21) +#define GUSBCFG_TSDPS BIT(22) +#define GUSBCFG_PCCI BIT(23) +#define GUSBCFG_PTCI BIT(24) +#define GUSBCFG_ULPIIPD BIT(25) +#define GUSBCFG_TSDPS BIT(22) #define GRSTCTL_CSFTRST (1 << GC_USB_GRSTCTL_CSFTRST_LSB) @@ -313,12 +313,12 @@ extern struct dwc_usb usb_ctl; #define DOEPDMA_BS_HOST_BSY (3 << 30) #define DOEPDMA_BS_MASK (3 << 30) #define DOEPDMA_RXSTS_MASK (3 << 28) -#define DOEPDMA_LAST (1 << 27) -#define DOEPDMA_SP (1 << 26) -#define DOEPDMA_IOC (1 << 25) -#define DOEPDMA_SR (1 << 24) -#define DOEPDMA_MTRF (1 << 23) -#define DOEPDMA_NAK (1 << 16) +#define DOEPDMA_LAST BIT(27) +#define DOEPDMA_SP BIT(26) +#define DOEPDMA_IOC BIT(25) +#define DOEPDMA_SR BIT(24) +#define DOEPDMA_MTRF BIT(23) +#define DOEPDMA_NAK BIT(16) #define DOEPDMA_RXBYTES(n) (((n) & 0xFFFF) << 0) #define DOEPDMA_RXBYTES_MASK (0xFFFF << 0) @@ -328,9 +328,9 @@ extern struct dwc_usb usb_ctl; #define DIEPDMA_BS_HOST_BSY (3 << 30) #define DIEPDMA_BS_MASK (3 << 30) #define DIEPDMA_TXSTS_MASK (3 << 28) -#define DIEPDMA_LAST (1 << 27) -#define DIEPDMA_SP (1 << 26) -#define DIEPDMA_IOC (1 << 25) +#define DIEPDMA_LAST BIT(27) +#define DIEPDMA_SP BIT(26) +#define DIEPDMA_IOC BIT(25) #define DIEPDMA_TXBYTES(n) (((n) & 0xFFFF) << 0) #define DIEPDMA_TXBYTES_MASK (0xFFFF << 0) @@ -942,31 +942,31 @@ extern struct dwc_usb usb_ctl; #define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc #define GC_USB_GUSBCFG_PCCI_LSB 23 -#define GC_USB_GUSBCFG_PCCI_MASK (1 << 23) +#define GC_USB_GUSBCFG_PCCI_MASK BIT(23) #define GC_USB_GUSBCFG_PCCI_SIZE 0x1 #define GC_USB_GUSBCFG_PCCI_DEFAULT 0x0 #define GC_USB_GUSBCFG_PCCI_OFFSET 0xc #define GC_USB_GUSBCFG_PTCI_LSB 24 -#define GC_USB_GUSBCFG_PTCI_MASK (1 << 24) +#define GC_USB_GUSBCFG_PTCI_MASK BIT(24) #define GC_USB_GUSBCFG_PTCI_SIZE 0x1 #define GC_USB_GUSBCFG_PTCI_DEFAULT 0x0 #define GC_USB_GUSBCFG_PTCI_OFFSET 0xc #define GC_USB_GUSBCFG_ULPIIPD_LSB 25 -#define GC_USB_GUSBCFG_ULPIIPD_MASK (1 << 25) +#define GC_USB_GUSBCFG_ULPIIPD_MASK BIT(25) #define GC_USB_GUSBCFG_ULPIIPD_SIZE 0x1 #define GC_USB_GUSBCFG_ULPIIPD_DEFAULT 0x0 #define GC_USB_GUSBCFG_ULPIIPD_OFFSET 0xc #define GC_USB_GUSBCFG_FHMOD_LSB 29 -#define GC_USB_GUSBCFG_FHMOD_MASK (1 << 29) +#define GC_USB_GUSBCFG_FHMOD_MASK BIT(29) #define GC_USB_GUSBCFG_FHMOD_SIZE 0x1 #define GC_USB_GUSBCFG_FHMOD_DEFAULT 0x0 #define GC_USB_GUSBCFG_FHMOD_OFFSET 0xc #define GC_USB_GUSBCFG_FDMOD_LSB 30 -#define GC_USB_GUSBCFG_FDMOD_MASK (1 << 30) +#define GC_USB_GUSBCFG_FDMOD_MASK BIT(30) #define GC_USB_GUSBCFG_FDMOD_SIZE 0x1 #define GC_USB_GUSBCFG_FDMOD_DEFAULT 0x0 #define GC_USB_GUSBCFG_FDMOD_OFFSET 0xc diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c index 8c6ecca110..92656a1582 100644 --- a/chip/stm32/usb_pd_phy.c +++ b/chip/stm32/usb_pd_phy.c @@ -176,7 +176,7 @@ int pd_find_preamble(int port) } } cnt = vals[bit] - vals[bit-1]; - all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? 1 << 31 : 0); + all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0); if (all == 0x36db6db6) return bit - 1; /* should be SYNC-1 */ if (all == 0xF33F3F3F) @@ -557,7 +557,7 @@ void pd_hw_init_rx(int port) /* --- DAC configuration for comparator at 850mV --- */ #ifdef CONFIG_PD_USE_DAC_AS_REF /* Enable DAC interface clock. */ - STM32_RCC_APB1ENR |= (1 << 29); + STM32_RCC_APB1ENR |= BIT(29); /* Delay 1 APB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_APB, 1); /* set voltage Vout=0.850V (Vref = 3.0V) */ @@ -570,7 +570,7 @@ void pd_hw_init_rx(int port) #ifdef CONFIG_USB_PD_INTERNAL_COMP #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) /* turn on COMP/SYSCFG */ - STM32_RCC_APB2ENR |= 1 << 0; + STM32_RCC_APB2ENR |= BIT(0); /* Delay 1 APB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_APB, 1); /* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */ @@ -583,12 +583,12 @@ void pd_hw_init_rx(int port) CMP2OUTSEL | STM32_COMP_CMP2HYST_HI; #elif defined(CHIP_FAMILY_STM32L) - STM32_RCC_APB1ENR |= 1 << 31; /* turn on COMP */ + STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */ STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1 | STM32_COMP_SPEED_FAST; /* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */ - STM32_RI_ASCR2 |= 1 << 4; + STM32_RI_ASCR2 |= BIT(4); #else #error Unsupported chip family #endif @@ -641,7 +641,7 @@ void pd_hw_init(int port, int role) /* 50% duty cycle on the output */ phy->tim_tx->ccr[TIM_TX_CCR_IDX(port)] = phy->tim_tx->arr / 2; /* Timer channel output configuration */ - val = (6 << 4) | (1 << 3); + val = (6 << 4) | BIT(3); if ((TIM_TX_CCR_IDX(port) & 1) == 0) /* CH2 or CH4 */ val <<= 8; if (TIM_TX_CCR_IDX(port) <= 2) |