cleanup: fix all the header guards

This unifies all the EC header files to use __CROS_EC_FILENAME_H
as the include guard. Well, except for test/ util/ and extra/
which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively.

BUG=chromium:496895
BRANCH=none
TEST=make buildall -j

Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029
Reviewed-on: https://chromium-review.googlesource.com/278121
Reviewed-by: Randall Spangler <rspangler@chromium.org>

27 files changed, 80 insertions, 80 deletions

diff --git a/chip/g/cr50_a1_regdefs.h b/chip/g/cr50_a1_regdefs.h
index da28c39076..62abc4135b 100644
--- a/chip/g/cr50_a1_regdefs.h
+++ b/chip/g/cr50_a1_regdefs.h
@@ -6,8 +6,8 @@
 
 /* This file is autogenerated. Do not edit. */
 
-#ifndef GC_REGDEFS_H
-#define GC_REGDEFS_H
+#ifndef __CROS_EC_CR50_A1_REGDEFS_H
+#define __CROS_EC_CR50_A1_REGDEFS_H
 #define GC___REVA__                              1
 #define GC___REVB__                              2
 #define GC___REVC__                              3
@@ -18354,7 +18354,7 @@
   -1
 #endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */
 
-#endif /* GC_REGDEFS_H */
+#endif /* __CROS_EC_CR50_A1_REGDEFS_H */
 #define GC_CONST_FSH_PE_CONTROL_READ             0x16021765
 #define GC_CONST_FSH_PE_CONTROL_PROGRAM          0x27182818
 #define GC_CONST_FSH_PE_CONTROL_ERASE            0x31415927
diff --git a/chip/g/cr50_fpga_regdefs.h b/chip/g/cr50_fpga_regdefs.h
index cfe8dd8f59..e6b3d4775c 100644
--- a/chip/g/cr50_fpga_regdefs.h
+++ b/chip/g/cr50_fpga_regdefs.h
@@ -6,8 +6,8 @@
 
 /* This file is autogenerated. Do not edit. */
 
-#ifndef GC_REGDEFS_H
-#define GC_REGDEFS_H
+#ifndef __CROS_EC_CR50_FPGA_REGDEFS_H
+#define __CROS_EC_CR50_FPGA_REGDEFS_H
 #define GC___REVA__                              1
 #define GC___REVB__                              2
 #define GC___REVC__                              3
@@ -18211,7 +18211,7 @@
   -1
 #endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */
 
-#endif /* GC_REGDEFS_H */
+#endif /* __CROS_EC_CR50_FPGA_REGDEFS_H */
 #define GC_CONST_FSH_PE_CONTROL_READ             0x16021765
 #define GC_CONST_FSH_PE_CONTROL_PROGRAM          0x27182818
 #define GC_CONST_FSH_PE_CONTROL_ERASE            0x31415927
diff --git a/chip/g/pmu.h b/chip/g/pmu.h
index 7411735850..db832184df 100644
--- a/chip/g/pmu.h
+++ b/chip/g/pmu.h
@@ -3,8 +3,8 @@
  * found in the LICENSE file.
  */
 
-#ifndef INC_PMU_H_
-#define INC_PMU_H_
+#ifndef __CROS_EC_PMU_H
+#define __CROS_EC_PMU_H
 
 #include "common.h"
 #include "registers.h"
@@ -110,4 +110,4 @@ extern void pmu_powerdown_exit(void);
  * enable clock doubler for USB purposes
  */
 void pmu_enable_clock_doubler(void);
-#endif /* INC_PMU_H_ */
+#endif /* __CROS_EC_PMU_H */
diff --git a/chip/host/persistence.h b/chip/host/persistence.h
index 0a80c2e618..1fab1c8235 100644
--- a/chip/host/persistence.h
+++ b/chip/host/persistence.h
@@ -5,8 +5,8 @@
 
 /* Persistence module for emulator */
 
-#ifndef _PERSISTENCE_H
-#define _PERSISTENCE_H
+#ifndef __CROS_EC_PERSISTENCE_H
+#define __CROS_EC_PERSISTENCE_H
 
 #include <stdio.h>
 
@@ -16,4 +16,4 @@ void release_persistent_storage(FILE *ps);
 
 void remove_persistent_storage(const char *tag);
 
-#endif /* _PERSISTENCE_H */
+#endif /* __CROS_EC_PERSISTENCE_H */
diff --git a/chip/host/reboot.h b/chip/host/reboot.h
index b6a7d817e6..e391866497 100644
--- a/chip/host/reboot.h
+++ b/chip/host/reboot.h
@@ -5,8 +5,8 @@
 
 /* Emulator self-reboot procedure */
 
-#ifndef __REBOOT_H
-#define __REBOOT_H
+#ifndef __CROS_EC_REBOOT_H
+#define __CROS_EC_REBOOT_H
 
 void emulator_reboot(void);
 
diff --git a/chip/it83xx/ec2i_chip.h b/chip/it83xx/ec2i_chip.h
index d584973ef7..953903226b 100644
--- a/chip/it83xx/ec2i_chip.h
+++ b/chip/it83xx/ec2i_chip.h
@@ -5,8 +5,8 @@
 
 /* EC2I control module for IT83xx. */
 
-#ifndef __CROS_EC_IT83XX_EC2I_H
-#define __CROS_EC_IT83XX_EC2I_H
+#ifndef __CROS_EC_EC2I_CHIP_H
+#define __CROS_EC_EC2I_CHIP_H
 
 /* Index list of the host interface registers of PNPCFG */
 enum host_pnpcfg_index {
@@ -123,4 +123,4 @@ enum ec2i_message ec2i_write(enum host_pnpcfg_index index, uint8_t data);
 /* EC2I read */
 enum ec2i_message ec2i_read(enum host_pnpcfg_index index);
 
-#endif /* __CROS_EC_IT83XX_EC2I_H */
+#endif /* __CROS_EC_EC2I_CHIP_H */
diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h
index 8d125eb943..274c1a129a 100644
--- a/chip/it83xx/intc.h
+++ b/chip/it83xx/intc.h
@@ -5,8 +5,8 @@
 
 /* INTC control module for IT83xx. */
 
-#ifndef __CROS_EC_IT83XX_INTC_H
-#define __CROS_EC_IT83XX_INTC_H
+#ifndef __CROS_EC_INTC_H
+#define __CROS_EC_INTC_H
 
 void lpc_kbc_ibf_interrupt(void);
 void lpc_kbc_obe_interrupt(void);
@@ -17,4 +17,4 @@ void pm4_ibf_interrupt(void);
 void pm5_ibf_interrupt(void);
 void lpcrst_interrupt(enum gpio_signal signal);
 
-#endif /* __CROS_EC_IT83XX_INTC_H */
+#endif /* __CROS_EC_INTC_H */
diff --git a/chip/it83xx/kmsc_chip.h b/chip/it83xx/kmsc_chip.h
index 348cf34204..cf4169a1c4 100644
--- a/chip/it83xx/kmsc_chip.h
+++ b/chip/it83xx/kmsc_chip.h
@@ -5,9 +5,9 @@
 
 /* Keyboard matrix scan control module for IT83xx. */
 
-#ifndef __CROS_EC_IT83XX_KMSC_H
-#define __CROS_EC_IT83XX_KMSC_H
+#ifndef __CROS_EC_KMSC_CHIP_H
+#define __CROS_EC_KMSC_CHIP_H
 
 void keyboard_raw_interrupt(void);
 
-#endif /* __CROS_EC_IT83XX_KMSC_H */
+#endif /* __CROS_EC_KMSC_CHIP_H */
diff --git a/chip/it83xx/pwm_chip.h b/chip/it83xx/pwm_chip.h
index d3c31a53fb..3c17b00125 100644
--- a/chip/it83xx/pwm_chip.h
+++ b/chip/it83xx/pwm_chip.h
@@ -5,8 +5,8 @@
 
 /* PWM control module for IT83xx. */
 
-#ifndef __CROS_EC_IT83XX_PWM_H
-#define __CROS_EC_IT83XX_PWM_H
+#ifndef __CROS_EC_PWM_CHIP_H
+#define __CROS_EC_PWM_CHIP_H
 
 /* Data structure to define PWM channel control registers. */
 struct pwm_ctrl_t {
@@ -42,4 +42,4 @@ struct pwm_t {
 
 extern const struct pwm_t pwm_channels[];
 
-#endif /* __CROS_EC_IT83XX_PWM_H */
+#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/lm4/pwm_chip.h b/chip/lm4/pwm_chip.h
index ac83fcf7da..a30457b629 100644
--- a/chip/lm4/pwm_chip.h
+++ b/chip/lm4/pwm_chip.h
@@ -5,8 +5,8 @@
 
 /* LM4-specific PWM module for Chrome EC */
 
-#ifndef __CROS_EC_LM4_PWM_H
-#define __CROS_EC_LM4_PWM_H
+#ifndef __CROS_EC_PWM_CHIP_H
+#define __CROS_EC_PWM_CHIP_H
 
 /* Data structure to define PWM channels. */
 struct pwm_t {
@@ -18,4 +18,4 @@ struct pwm_t {
 
 extern const struct pwm_t pwm_channels[];
 
-#endif /* __CROS_EC_LM4_PWM_H */
+#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/mec1322/pwm_chip.h b/chip/mec1322/pwm_chip.h
index 7c59b1004f..8ffdbef5b6 100644
--- a/chip/mec1322/pwm_chip.h
+++ b/chip/mec1322/pwm_chip.h
@@ -4,8 +4,8 @@
  */
 
 /* MEC1322-specific PWM module for Chrome EC */
-#ifndef __CROS_EC_MEC1322_PWM_H
-#define __CROS_EC_MEC1322_PWM_H
+#ifndef __CROS_EC_PWM_CHIP_H
+#define __CROS_EC_PWM_CHIP_H
 
 /* Data structure to define PWM channels. */
 struct pwm_t {
@@ -18,4 +18,4 @@ struct pwm_t {
 
 extern const struct pwm_t pwm_channels[];
 
-#endif  /* __CROS_EC_MEC1322_PWM_H */
+#endif  /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/npcx/clock_chip.h b/chip/npcx/clock_chip.h
index ffc5958869..3b2b847dc0 100644
--- a/chip/npcx/clock_chip.h
+++ b/chip/npcx/clock_chip.h
@@ -5,8 +5,8 @@
 
 /* NPCX-specific clock module for Chrome EC */
 
-#ifndef CLOCK_CHIP_H_
-#define CLOCK_CHIP_H_
+#ifndef __CROS_EC_CLOCK_CHIP_H
+#define __CROS_EC_CLOCK_CHIP_H
 
 /**
  * Return the current APB1 clock frequency in Hz.
@@ -18,4 +18,4 @@ int clock_get_apb1_freq(void);
  */
 int clock_get_apb2_freq(void);
 
-#endif /* CLOCK_CHIP_H_ */
+#endif /* __CROS_EC_CLOCK_CHIP_H */
diff --git a/chip/npcx/fan_chip.h b/chip/npcx/fan_chip.h
index b6af2a7c2e..02c86bc9d4 100644
--- a/chip/npcx/fan_chip.h
+++ b/chip/npcx/fan_chip.h
@@ -5,8 +5,8 @@
 
 /* NPCX-specific MFT module for Chrome EC */
 
-#ifndef __CROS_EC_NPCX_FAN_H
-#define __CROS_EC_NPCX_FAN_H
+#ifndef __CROS_EC_FAN_CHIP_H
+#define __CROS_EC_FAN_CHIP_H
 
 /* MFT module select */
 enum npcx_mft_module {
@@ -59,4 +59,4 @@ struct tacho_status_t {
 
 extern const struct mft_t mft_channels[];
 
-#endif /* __CROS_EC_NPCX_FAN_H */
+#endif /* __CROS_EC_FAN_CHIP_H */
diff --git a/chip/npcx/hwtimer_chip.h b/chip/npcx/hwtimer_chip.h
index 490d67b80d..732ef8fac4 100644
--- a/chip/npcx/hwtimer_chip.h
+++ b/chip/npcx/hwtimer_chip.h
@@ -5,8 +5,8 @@
 
 /* NPCX-specific hwtimer module for Chrome EC */
 
-#ifndef HWTIMER_CHIP_H_
-#define HWTIMER_CHIP_H_
+#ifndef __CROS_EC_HWTIMER_CHIP_H
+#define __CROS_EC_HWTIMER_CHIP_H
 
 /* Channel definition for ITIM16 */
 #define ITIM_TIME_NO	ITIM16_1
@@ -25,4 +25,4 @@ void init_hw_timer(int itim_no, enum ITIM16_SOURCE_CLOCK_T source);
 /* Returns time delay cause of deep idle */
 uint32_t __hw_clock_get_sleep_time(void);
 
-#endif /* HWTIMER_CHIP_H_ */
+#endif /* __CROS_EC_HWTIMER_CHIP_H */
diff --git a/chip/npcx/lfw/ec_lfw.h b/chip/npcx/lfw/ec_lfw.h
index 857135d6d0..a1a02b5f6f 100644
--- a/chip/npcx/lfw/ec_lfw.h
+++ b/chip/npcx/lfw/ec_lfw.h
@@ -5,8 +5,8 @@
  * NPCX5M5G SoC little FW used by booter
  */
 
-#ifndef __CROS_EC_LFW_H_
-#define __CROS_EC_LFW_H_
+#ifndef __CROS_EC_EC_LFW_H
+#define __CROS_EC_EC_LFW_H
 
 /* Begin address for the .iram section; defined in linker script */
 extern unsigned int __iram_fw_start;
@@ -15,4 +15,4 @@ extern unsigned int __iram_fw_end;
 /* Begin address for the iram codes; defined in linker script */
 extern unsigned int __flash_fw_start;
 
-#endif /* __CROS_EC_LFW_H_ */
+#endif /* __CROS_EC_EC_LFW_H */
diff --git a/chip/npcx/pwm_chip.h b/chip/npcx/pwm_chip.h
index 77d6991c7b..201f628106 100644
--- a/chip/npcx/pwm_chip.h
+++ b/chip/npcx/pwm_chip.h
@@ -5,8 +5,8 @@
 
 /* NPCX-specific PWM module for Chrome EC */
 
-#ifndef __CROS_EC_NPCX_PWM_H
-#define __CROS_EC_NPCX_PWM_H
+#ifndef __CROS_EC_PWM_CHIP_H
+#define __CROS_EC_PWM_CHIP_H
 
 /* Data structure to define PWM channels. */
 struct pwm_t {
@@ -23,4 +23,4 @@ struct pwm_t {
 extern const struct pwm_t pwm_channels[];
 void pwm_config(enum pwm_channel ch);
 
-#endif /* __CROS_EC_NPCX_PWM_H */
+#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h
index 135e2f1cd8..2cafb9649f 100644
--- a/chip/npcx/system_chip.h
+++ b/chip/npcx/system_chip.h
@@ -5,8 +5,8 @@
 
 /* NPCX-specific SIB module for Chrome EC */
 
-#ifndef __CROS_EC_NPCX_LPC_H
-#define __CROS_EC_NPCX_LPC_H
+#ifndef __CROS_EC_SYSTEM_CHIP_H
+#define __CROS_EC_SYSTEM_CHIP_H
 
 /* Indices for battery-backed ram (BBRAM) data position */
 enum bbram_data_index {
@@ -32,4 +32,4 @@ extern unsigned int __flash_lpfw_start;
 /* End flash address for the lpram codes; defined in linker script */
 extern unsigned int __flash_lpfw_end;
 
-#endif /* __CROS_EC_NPCX_LPC_H */
+#endif /* __CROS_EC_SYSTEM_CHIP_H */
diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h
index edaf3b5d32..d6959310d6 100644
--- a/chip/stm32/crc_hw.h
+++ b/chip/stm32/crc_hw.h
@@ -3,8 +3,8 @@
  * found in the LICENSE file.
  */
 
-#ifndef _CRC_HW_H
-#define _CRC_HW_H
+#ifndef __CROS_EC_CRC_HW_H
+#define __CROS_EC_CRC_HW_H
 /* CRC-32 hardware implementation with USB constants */
 
 #include "clock.h"
@@ -38,4 +38,4 @@ static inline uint32_t crc32_result(void)
 	return STM32_CRC_DR ^ 0xFFFFFFFF;
 }
 
-#endif /* _CRC_HW_H */
+#endif /* __CROS_EC_CRC_HW_H */
diff --git a/chip/stm32/pwm_chip.h b/chip/stm32/pwm_chip.h
index 4e15e612c1..ac30f645ee 100644
--- a/chip/stm32/pwm_chip.h
+++ b/chip/stm32/pwm_chip.h
@@ -5,8 +5,8 @@
 
 /* STM32-specific PWM module for Chrome EC */
 
-#ifndef __CROS_EC_STM32_PWM_H
-#define __CROS_EC_STM32_PWM_H
+#ifndef __CROS_EC_PWM_CHIP_H
+#define __CROS_EC_PWM_CHIP_H
 
 /* Data structure to define PWM channels. */
 struct pwm_t {
@@ -36,4 +36,4 @@ extern const struct pwm_t pwm_channels[];
 /* Plain ID mapping for readability */
 #define STM32_TIM_CH(x) (x)
 
-#endif /* __CROS_EC_STM32_PWM_H */
+#endif /* __CROS_EC_PWM_CHIP_H */
diff --git a/chip/stm32/usart-stm32f.h b/chip/stm32/usart-stm32f.h
index e576c007b3..5b0abe0a01 100644
--- a/chip/stm32/usart-stm32f.h
+++ b/chip/stm32/usart-stm32f.h
@@ -2,8 +2,8 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#ifndef CHIP_STM32_USART_STM32F_H
-#define CHIP_STM32_USART_STM32F_H
+#ifndef __CROS_EC_USART_STM32F_H
+#define __CROS_EC_USART_STM32F_H
 
 #include "usart.h"
 
@@ -17,4 +17,4 @@ extern struct usart_hw_config const usart1_hw;
 extern struct usart_hw_config const usart2_hw;
 extern struct usart_hw_config const usart3_hw;
 
-#endif /* CHIP_STM32_USART_STM32F_H */
+#endif /* __CROS_EC_USART_STM32F_H */
diff --git a/chip/stm32/usart-stm32f0.h b/chip/stm32/usart-stm32f0.h
index f87d0dc590..4c4e9ad93e 100644
--- a/chip/stm32/usart-stm32f0.h
+++ b/chip/stm32/usart-stm32f0.h
@@ -2,8 +2,8 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#ifndef CHIP_STM32_USART_STM32F0_H
-#define CHIP_STM32_USART_STM32F0_H
+#ifndef __CROS_EC_USART_STM32F0_H
+#define __CROS_EC_USART_STM32F0_H
 
 #include "usart.h"
 
@@ -18,4 +18,4 @@ extern struct usart_hw_config const usart2_hw;
 extern struct usart_hw_config const usart3_hw;
 extern struct usart_hw_config const usart4_hw;
 
-#endif /* CHIP_STM32_USART_STM32F0_H */
+#endif /* __CROS_EC_USART_STM32F0_H */
diff --git a/chip/stm32/usart-stm32f3.h b/chip/stm32/usart-stm32f3.h
index ebf972aab9..9399b339a2 100644
--- a/chip/stm32/usart-stm32f3.h
+++ b/chip/stm32/usart-stm32f3.h
@@ -2,8 +2,8 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#ifndef CHIP_STM32_USART_STM32F3_H
-#define CHIP_STM32_USART_STM32F3_H
+#ifndef __CROS_EC_USART_STM32F3_H
+#define __CROS_EC_USART_STM32F3_H
 
 #include "usart.h"
 
@@ -17,4 +17,4 @@ extern struct usart_hw_config const usart1_hw;
 extern struct usart_hw_config const usart2_hw;
 extern struct usart_hw_config const usart3_hw;
 
-#endif /* CHIP_STM32_USART_STM32F3_H */
+#endif /* __CROS_EC_USART_STM32F3_H */
diff --git a/chip/stm32/usart-stm32l.h b/chip/stm32/usart-stm32l.h
index 2011a6517d..ca97bb0912 100644
--- a/chip/stm32/usart-stm32l.h
+++ b/chip/stm32/usart-stm32l.h
@@ -2,8 +2,8 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#ifndef CHIP_STM32_USART_STM32L_H
-#define CHIP_STM32_USART_STM32L_H
+#ifndef __CROS_EC_USART_STM32L_H
+#define __CROS_EC_USART_STM32L_H
 
 #include "usart.h"
 
@@ -17,4 +17,4 @@ extern struct usart_hw_config const usart1_hw;
 extern struct usart_hw_config const usart2_hw;
 extern struct usart_hw_config const usart3_hw;
 
-#endif /* CHIP_STM32_USART_STM32L_H */
+#endif /* __CROS_EC_USART_STM32L_H */
diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h
index 79a87331bd..625f6e970f 100644
--- a/chip/stm32/usart.h
+++ b/chip/stm32/usart.h
@@ -2,8 +2,8 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#ifndef CHIP_STM32_USART_H
-#define CHIP_STM32_USART_H
+#ifndef __CROS_EC_USART_H
+#define __CROS_EC_USART_H
 
 /* STM32 USART driver for Chrome EC */
 
@@ -158,4 +158,4 @@ void usart_interrupt(struct usart_config const *config);
 void usart_set_baud_f0_l(struct usart_config const *config, int frequency_hz);
 void usart_set_baud_f(struct usart_config const *config, int frequency_hz);
 
-#endif /* CHIP_STM32_USART_H */
+#endif /* __CROS_EC_USART_H */
diff --git a/chip/stm32/usb-stream.h b/chip/stm32/usb-stream.h
index 97816afa05..c99fd3e695 100644
--- a/chip/stm32/usb-stream.h
+++ b/chip/stm32/usb-stream.h
@@ -2,8 +2,8 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#ifndef CHIP_STM32_USB_STREAM_H
-#define CHIP_STM32_USB_STREAM_H
+#ifndef __CROS_EC_USB_STREAM_H
+#define __CROS_EC_USB_STREAM_H
 
 /* STM32 USB STREAM driver for Chrome EC */
 
@@ -206,4 +206,4 @@ void usb_stream_tx(struct usb_stream_config const *config);
 void usb_stream_rx(struct usb_stream_config const *config);
 void usb_stream_reset(struct usb_stream_config const *config);
 
-#endif /* CHIP_STM32_USB_STREAM_H */
+#endif /* __CROS_EC_USB_STREAM_H */
diff --git a/chip/stm32/usb_gpio.h b/chip/stm32/usb_gpio.h
index 56f3d72c57..1bddf65734 100644
--- a/chip/stm32/usb_gpio.h
+++ b/chip/stm32/usb_gpio.h
@@ -2,8 +2,8 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#ifndef CHIP_STM32_USB_GPIO_H
-#define CHIP_STM32_USB_GPIO_H
+#ifndef __CROS_EC_USB_GPIO_H
+#define __CROS_EC_USB_GPIO_H
 
 /* STM32 USB GPIO driver for Chrome EC */
 
@@ -125,4 +125,4 @@ void usb_gpio_tx(struct usb_gpio_config const *config);
 void usb_gpio_rx(struct usb_gpio_config const *config);
 void usb_gpio_reset(struct usb_gpio_config const *config);
 
-#endif /* CHIP_STM32_USB_GPIO_H */
+#endif /* __CROS_EC_USB_GPIO_H */
diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h
index 76719c6d2c..615bbf663e 100644
--- a/chip/stm32/usb_spi.h
+++ b/chip/stm32/usb_spi.h
@@ -2,8 +2,8 @@
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
-#ifndef CHIP_STM32_USB_SPI_H
-#define CHIP_STM32_USB_SPI_H
+#ifndef __CROS_EC_USB_SPI_H
+#define __CROS_EC_USB_SPI_H
 
 /* STM32 USB SPI driver for Chrome EC */
 
@@ -233,4 +233,4 @@ int  usb_spi_interface(struct usb_spi_config const *config,
 void usb_spi_board_enable(struct usb_spi_config const *config);
 void usb_spi_board_disable(struct usb_spi_config const *config);
 
-#endif /* CHIP_STM32_USB_SPI_H */
+#endif /* __CROS_EC_USB_SPI_H */