diff options
| author | Edward Hill <ecgh@chromium.org> | 2020-12-15 14:33:53 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-12-16 13:09:43 +0000 |
| commit | 57a42eb41ab26bca5d2edd6a3ff1ba2aaeb0fabf (patch) | |
| tree | e9d5d519a92502a20a9fdade54fd25547a0ab8c6 /chip | |
| parent | ca948d79a7030df97b8f4fea16292b60fa60fd03 (diff) | |
| download | chrome-ec-57a42eb41ab26bca5d2edd6a3ff1ba2aaeb0fabf.tar.gz | |
npcx: Don't delay hibernate wake by 2 seconds (v2)
Revert CL:2576439 and try again, this time checking for
EC_RESET_FLAG_HIBERNATE before setting EC_RESET_FLAG_INITIAL_PWR.
The problem with the first attempt was on sysjump to RW after wake
from hibernate. Then gpio_pre_init() saw EC_RESET_FLAG_INITIAL_PWR
but not EC_RESET_FLAG_HIBERNATE and so added an unwanted 2 second
delay because system_common_pre_init() hadn't yet restored the flags
from before the jump. Moving the check for EC_RESET_FLAG_HIBERNATE
into check_reset_cause() avoids this issue.
BUG=b:173180800
BRANCH=zork
TEST=no 2 second delay on wake from hibernate, for both RO boot
and jump to RW.
Signed-off-by: Edward Hill <ecgh@chromium.org>
Change-Id: Ia1bfba5740d77961ccc7e140da80be1070700b1e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592501
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/npcx/gpio.c | 6 | ||||
| -rw-r--r-- | chip/npcx/system.c | 17 |
2 files changed, 12 insertions, 11 deletions
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index dca7168009..23f4450ff7 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -524,14 +524,10 @@ void gpio_pre_init(void) * reset (2) will happen before the end of the delay so we avoid extra * output toggles. * - * Waking from PSL hibernate is power-on for EC but not for H1, so - * do not add delay. - * * Make sure to set up the timer before using udelay(). */ if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) && - system_get_reset_flags() & EC_RESET_FLAG_INITIAL_PWR - && !(system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE)) { + system_get_reset_flags() & EC_RESET_FLAG_INITIAL_PWR) { __hw_early_init_hwtimer(0); udelay(2 * SECOND); /* Shouldn't get here, but proceeding anyway... */ diff --git a/chip/npcx/system.c b/chip/npcx/system.c index e74ae65d58..a779c050bf 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -378,6 +378,8 @@ static void check_reset_cause(void) /* Clear saved hibernate wake flag in bbram , too */ bbram_data_write(BBRM_DATA_INDEX_WAKE, 0); + chip_set_hib_flag(&flags, hib_wake_flags); + /* Use scratch bit to check power on reset or VCC1_RST reset */ if (!IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH)) { #ifdef CONFIG_BOARD_FORCE_RESET_PIN @@ -419,15 +421,20 @@ static void check_reset_cause(void) */ flags |= EC_RESET_FLAG_RESET_PIN; } else { + flags |= EC_RESET_FLAG_POWER_ON; + /* * Power-on restart, so set a flag and save it * for the next imminent reset. Later code * will check for this flag and wait for the - * second reset. + * second reset. Waking from PSL hibernate is + * power-on for EC but not for H1, so do not + * wait for the second reset. */ - flags |= EC_RESET_FLAG_POWER_ON - | EC_RESET_FLAG_INITIAL_PWR; - chip_flags |= EC_RESET_FLAG_INITIAL_PWR; + if (!(flags & EC_RESET_FLAG_HIBERNATE)) { + flags |= EC_RESET_FLAG_INITIAL_PWR; + chip_flags |= EC_RESET_FLAG_INITIAL_PWR; + } } } else /* @@ -454,8 +461,6 @@ static void check_reset_cause(void) SET_BIT(NPCX_RSTCTL, NPCX_RSTCTL_DBGRST_STS); } - chip_set_hib_flag(&flags, hib_wake_flags); - /* Watchdog Reset */ if (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS)) { /* |