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| author | Mulin Chao <mlchao@nuvoton.com> | 2017-10-17 17:36:09 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-10-29 21:55:25 -0700 |
| commit | 32cc460bad5ad02a4b7e0a85ef54361049e80897 (patch) | |
| tree | d64ee1189862dc992384071ca71bb5aa14351dbf /chip | |
| parent | 18f4a483f073b3a8f64f1da2e1089f658e1dbba6 (diff) | |
| download | chrome-ec-32cc460bad5ad02a4b7e0a85ef54361049e80897.tar.gz | |
npcx: espi: fixed bug that ec cannot wakeup from deep idle by VW events
According npcx ec wake-up mechanism by espi VW events, the driver
needs to make sure the IE/WE bits in VWEVMSn and the VWUPD bit in
ESPIWE registers are both set. Or ec won't wakeup by VW signals until
the other wake-up events occured. (WE bit of VWEVMSn is introduced on
npcx7.)
In this CL, we turn on IE/WE bit in VWEVMSn registers during espi driver
initialization and toggle the bits of ESPIWE register for VW and general
events such as ESPI_RST and so on when ec turn on/off host interface's
interrupts to make sure ec can wake-up from deep idle by espi events in
time.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c
1000" to do stress test and no symptom occurred on poppy. Both warmboot
and coldboot stress test for 5 hours and no symptom occurred on poppy.
Change-Id: I853532508bf9da5f3abc39e20ab848e659ca5e26
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/725559
Reviewed-by: Amit Maoz <amit.maoz@nuvoton.corp-partner.google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/npcx/espi.c | 14 | ||||
| -rw-r--r-- | chip/npcx/lpc.c | 6 |
2 files changed, 11 insertions, 9 deletions
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c index 6731546db0..b3194e9b0b 100644 --- a/chip/npcx/espi.c +++ b/chip/npcx/espi.c @@ -61,13 +61,13 @@ struct vw_event_t { /* Default settings of VWEVMS registers (Please refer Table.43/44) */ static const struct vwevms_config_t espi_in_list[] = { - /* IDX EN ENPL ENESP IE VW Event Bit 0 - 3 (M->S) */ - {0x02, 1, 0, 0, 0}, /* SLP_S3#, SLP_S4#, SLP_S5, Reserve */ - {0x03, 1, 0, 1, 0}, /* SUS_STAT#, PLTRST#, ORST_WARN, Reserve */ - {0x07, 1, 1, 1, 0}, /* HRST_WARN, SMIOUT#, NMIOUT#, Reserve */ - {0x41, 1, 0, 1, 0}, /* SUS_WARN#, SPWRDN_ACK, Reserve, SLP_A# */ - {0x42, 1, 0, 0, 0}, /* SLP_LAN#, SLP_WAN#, Reserve, Reserve */ - {0x47, 1, 1, 1, 0}, /* HOST_C10, Reserve, Reserve, Reserve */ + /* IDX EN ENPL ENESP IE/WE VW Event Bit 0 - 3 (M->S) */ + {0x02, 1, 0, 0, 1}, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ + {0x03, 1, 0, 1, 1}, /* SUS_STAT#, PLTRST#, ORST_WARN, Reserve */ + {0x07, 1, 1, 1, 1}, /* HRST_WARN, SMIOUT#, NMIOUT#, Reserve */ + {0x41, 1, 0, 1, 1}, /* SUS_WARN#, SPWRDN_ACK, Reserve, SLP_A# */ + {0x42, 1, 0, 0, 1}, /* SLP_LAN#, SLP_WAN#, Reserve, Reserve */ + {0x47, 1, 1, 1, 1}, /* HOST_C10, Reserve, Reserve, Reserve */ }; /* Default settings of VWEVSM registers (Please refer Table.43/44) */ diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 6bc07fedfb..3d03acf1dc 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -105,8 +105,9 @@ static void lpc_task_enable_irq(void) task_enable_irq(NPCX_IRQ_WKINTA_2); /* Virtual Wire: HOST_RST_WARN, SUS_WARN, SUS_PWRDN_ACK, SLP_A */ task_enable_irq(NPCX_IRQ_WKINTB_2); - /* Enable eSPI module interrupts */ + /* Enable eSPI module interrupts and wake-up functionalities */ NPCX_ESPIIE |= (ESPIIE_GENERIC | ESPIIE_VW); + NPCX_ESPIWE |= (ESPIWE_GENERIC | ESPIWE_VW); #endif } @@ -121,8 +122,9 @@ static void lpc_task_disable_irq(void) task_disable_irq(NPCX_IRQ_WKINTA_2); /* Virtual Wire: HOST_RST_WARN,SUS_WARN, SUS_PWRDN_ACK, SLP_A */ task_disable_irq(NPCX_IRQ_WKINTB_2); - /* Disable eSPI module interrupts */ + /* Disable eSPI module interrupts and wake-up functionalities */ NPCX_ESPIIE &= ~(ESPIIE_GENERIC | ESPIIE_VW); + NPCX_ESPIWE &= ~(ESPIWE_GENERIC | ESPIWE_VW); #endif } /** |