cleanup: Remove CDRAM / CODERAM CONFIGs

CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.

These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.

BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

8 files changed, 18 insertions, 18 deletions

diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
index 514f292914..2309baad60 100644
--- a/chip/mec1322/config_chip.h
+++ b/chip/mec1322/config_chip.h
@@ -100,7 +100,6 @@
 
 /* Program memory base address */
 #define CONFIG_PROGRAM_MEMORY_BASE	0x00100000
-#define CONFIG_CDRAM_BASE		0x00100000
 
 #include "config_flash_layout.h"
 
diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h
index 4a10175a02..0efa9d8345 100644
--- a/chip/mec1322/config_flash_layout.h
+++ b/chip/mec1322/config_flash_layout.h
@@ -15,7 +15,6 @@
  */
 
 /* Non-memmapped, external SPI */
-#define CONFIG_CODERAM_ARCH
 #define CONFIG_EXTERNAL_STORAGE
 #undef  CONFIG_MAPPED_STORAGE
 #undef  CONFIG_FLASH_PSTATE
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
index 56db32cc65..17e366ccfd 100644
--- a/chip/npcx/config_chip.h
+++ b/chip/npcx/config_chip.h
@@ -47,8 +47,6 @@
 /* Memory mapping */
 #define CONFIG_RAM_BASE            0x200C0000 /* memory address of data ram */
 #define CONFIG_RAM_SIZE            (0x00008000 - 0x800) /* 30KB data ram */
-#define CONFIG_CDRAM_BASE          0x100A8000 /* memory address of code ram */
-#define CONFIG_CDRAM_SIZE          0x00018000 /* 96KB code ram */
 #define CONFIG_PROGRAM_MEMORY_BASE 0x64000000 /* program memory base address */
 #define CONFIG_LPRAM_BASE          0x40001600 /* memory address of lpwr ram */
 #define CONFIG_LPRAM_SIZE	   0x00000620 /* 1568B low power ram */
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
index 986c0bbfea..9710d2b1e5 100644
--- a/chip/npcx/config_flash_layout.h
+++ b/chip/npcx/config_flash_layout.h
@@ -35,14 +35,14 @@
 
 /* RO firmware offset in flash */
 #define CONFIG_RO_MEM_OFF	CONFIG_RO_HDR_SIZE
-#define CONFIG_RO_SIZE		CONFIG_CDRAM_SIZE    /* 96KB for RO FW */
+#define CONFIG_RO_SIZE		(96 * 1024)   /* 96KB for RO FW */
 #define CONFIG_FLASH_SIZE	CONFIG_FLASH_PHYSICAL_SIZE
 
 /* RW firmware offset in flash */
 #define CONFIG_RW_MEM_OFF	CONFIG_RW_STORAGE_OFF
-#define CONFIG_RW_SIZE		CONFIG_CDRAM_SIZE    /* 96KB for RW FW */
+#define CONFIG_RW_SIZE		(96 * 1024)   /* 96KB for RW FW */
 
-/* The storage offset of ec.R*.flat which is used for CONFIG_CDRAM_ARCH */
+/* The storage offset of ec.R*.flat */
 #define CONFIG_RO_STORAGE_OFF	0
 #define CONFIG_RW_STORAGE_OFF	CONFIG_FW_IMAGE_SIZE /* 128 KB alignemnt */
 
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c
index c97c2b38cc..2bdcefe8a2 100644
--- a/chip/npcx/flash.c
+++ b/chip/npcx/flash.c
@@ -23,7 +23,7 @@ uint8_t flag_prot_inconsistent;
 
 #define FLASH_ABORT_TIMEOUT     10000
 
-#ifdef CONFIG_CODERAM_ARCH
+#ifdef CONFIG_EXTERNAL_STORAGE
 #define TRISTATE_FLASH(x)
 #else
 #define TRISTATE_FLASH(x) flash_tristate(x)
@@ -770,7 +770,7 @@ int flash_pre_init(void)
 	/* Enable FIU interface */
 	flash_pinmux(1);
 
-#ifdef CONFIG_CODERAM_ARCH
+#ifdef CONFIG_EXTERNAL_STORAGE
 	/* Disable tristate all the time */
 	CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
 #endif
diff --git a/chip/npcx/header.c b/chip/npcx/header.c
index ff0c50eb3b..49b7488b4f 100644
--- a/chip/npcx/header.c
+++ b/chip/npcx/header.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,8 +11,9 @@
  */
 
 #include <stdint.h>
+
+#include "config.h"
 #include "registers.h"
-#include "config_chip.h"
 
 /* Signature used by fw header */
 #define SIG_FW_EC           0x2A3B4D5E
@@ -24,7 +25,8 @@
 #define ERROR_DETECTION_DIS 0x00
 
 /* Code RAM addresses use by header */
-#define FW_START_ADDR  CONFIG_CDRAM_BASE /* Put FW at the begin of CODE RAM   */
+/* Put FW at the begin of CODE RAM */
+#define FW_START_ADDR  CONFIG_PROGRAM_MEMORY_BASE
 
 /* TODO: It will be filled automatically by ECST */
 /* The entry point of reset handler (filled by ECST tool)*/
diff --git a/chip/npcx/spiflashfw/ec_npcxflash.c b/chip/npcx/spiflashfw/ec_npcxflash.c
index cc97f69e5a..ef62ac97dc 100644
--- a/chip/npcx/spiflashfw/ec_npcxflash.c
+++ b/chip/npcx/spiflashfw/ec_npcxflash.c
@@ -6,8 +6,10 @@
  */
 
 #include <stdint.h>
+
+#include "config.h"
 #include "registers.h"
-#include "config_chip.h"
+#include "util.h"
 
 /*****************************************************************************/
 /* spi flash internal functions */
@@ -241,7 +243,7 @@ int sspi_flash_verify(int offset, int size, const char *data)
 int sspi_flash_get_image_used(const char *fw_base)
 {
 	const uint8_t *image;
-	int size = CONFIG_CDRAM_SIZE; /* maximum size is 128KB */
+	int size = MAX(CONFIG_RO_SIZE, CONFIG_RW_SIZE); /* max size is 128KB */
 
 	image = (const uint8_t *)fw_base;
 	/*
@@ -265,7 +267,7 @@ sspi_flash_upload(int spi_offset, int spi_size)
 	/*
 	 * Flash image has been uploaded to Code RAM
 	 */
-	const char *image_base = (const char *)CONFIG_CDRAM_BASE;
+	const char *image_base = (const char *)CONFIG_PROGRAM_MEMORY_BASE;
 	uint32_t sz_image = spi_size;
 
 	/* Unlock & stop watchdog */
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 23d66d7882..b6c23396b2 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -690,7 +690,7 @@ DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE,
 		system_rtc_set_value,
 		EC_VER_MASK(0));
 
-#ifdef CONFIG_CODERAM_ARCH
+#ifdef CONFIG_EXTERNAL_STORAGE
 void system_jump_to_booter(void)
 {
 	enum API_RETURN_STATUS_T status;
@@ -709,11 +709,11 @@ void system_jump_to_booter(void)
 
 	/* Make sure the reset vector is inside the destination image */
 	addr_entry = *(uintptr_t *)(flash_offset +
-				    CONFIG_PROGRAM_MEMORY_BASE + 4);
+				    CONFIG_MAPPED_STORAGE_BASE + 4);
 
 	download_from_flash(
 		flash_offset,      /* The offset of the data in spi flash */
-		CONFIG_CDRAM_BASE, /* The address of the downloaded data  */
+		CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */
 		flash_used,        /* Number of bytes to download      */
 		SIGN_NO_CHECK,     /* Need CRC check or not               */
 		addr_entry,        /* jump to this address after download */