diff options
author | Martin Roth <martinroth@chromium.org> | 2016-10-24 16:32:19 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2016-11-15 17:41:53 -0800 |
commit | 897ce78bddb26557a686ab9e756fcf3d6c121271 (patch) | |
tree | edde864d756a6e1133808118b8ae90c323ed4ade /chip | |
parent | 64b57efebdb311126f3daaa97d49443308507b76 (diff) | |
download | chrome-ec-897ce78bddb26557a686ab9e756fcf3d6c121271.tar.gz |
Fix various misspellings in comments
No functional changes.
BUG=none
BRANCH=none
TEST=make buildall passes
Change-Id: Ie852feb8e3951975d99dce5a49c17f5f0e8bc791
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/403417
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/g/sps.c | 12 | ||||
-rw-r--r-- | chip/g/sps_tpm.c | 2 | ||||
-rw-r--r-- | chip/g/usb.c | 2 | ||||
-rw-r--r-- | chip/lm4/gpio.c | 2 | ||||
-rw-r--r-- | chip/mec1322/clock.c | 2 | ||||
-rw-r--r-- | chip/mec1322/lpc.c | 4 | ||||
-rw-r--r-- | chip/npcx/hwtimer.c | 2 | ||||
-rw-r--r-- | chip/npcx/i2c.c | 4 | ||||
-rw-r--r-- | chip/npcx/lpc.c | 2 | ||||
-rw-r--r-- | chip/stm32/adc-stm32f0.c | 2 | ||||
-rw-r--r-- | chip/stm32/uart.c | 2 | ||||
-rw-r--r-- | chip/stm32/usart-stm32f0.c | 2 | ||||
-rw-r--r-- | chip/stm32/usart_rx_dma.h | 6 | ||||
-rw-r--r-- | chip/stm32/usart_tx_dma.h | 2 | ||||
-rw-r--r-- | chip/stm32/usb.c | 2 |
15 files changed, 24 insertions, 24 deletions
diff --git a/chip/g/sps.c b/chip/g/sps.c index 82336eb5a7..21558a6822 100644 --- a/chip/g/sps.c +++ b/chip/g/sps.c @@ -44,7 +44,7 @@ /* * Hardware pointers use one extra bit, which means that indexing FIFO and - * values written into the pointers have to have dfferent sizes. Tracked under + * values written into the pointers have to have different sizes. Tracked under * http://b/20894690 */ #define SPS_FIFO_PTR_MASK ((SPS_FIFO_MASK << 1) | 1) @@ -118,7 +118,7 @@ int sps_transmit(uint8_t *data, size_t data_size) /* * CR50 SPS controller does not allow byte * accesses for writes into the FIFO, so read - * modify/write is requred. Tracked uder + * modify/write is required. Tracked under * http://b/20894727 */ bit_shift = 8 * (wptr & 3); @@ -151,7 +151,7 @@ int sps_transmit(uint8_t *data, size_t data_size) /* * Start TX if necessary. This happens after FIFO is primed, which - * helps aleviate TX underrun problems but introduces delay before + * helps alleviate TX underrun problems but introduces delay before * data starts coming out. */ if (!GREAD_FIELD(SPS, FIFO_CTRL, TXFIFO_EN)) @@ -290,7 +290,7 @@ static void sps_advance_rx(int port, int data_size) /* * Actual receive interrupt processing function. Invokes the callback passing * it a pointer to the linear space in the RX FIFO and the number of bytes - * availabe at that address. + * available at that address. * * If RX fifo is wrapping around, the callback will be called twice with two * flat pointers. @@ -363,7 +363,7 @@ DECLARE_IRQ(GC_IRQNUM_SPS0_RXFIFO_LVL_INTR, _sps0_interrupt, 1); */ /* - * Receive callback implemets a simple state machine, it could be in one of + * Receive callback implements a simple state machine, it could be in one of * three states: not started, receiving frame, frame finished. */ @@ -483,7 +483,7 @@ static int command_sps(int argc, char **argv) /* * Wait for receive state machine to transition out of 'frame - * finised' state. + * finished' state. */ while (rx_state == spstrx_finished) { watchdog_reload(); diff --git a/chip/g/sps_tpm.c b/chip/g/sps_tpm.c index 771ae847b1..8658ffc041 100644 --- a/chip/g/sps_tpm.c +++ b/chip/g/sps_tpm.c @@ -131,7 +131,7 @@ static void init_new_cycle(void) enable_sleep(SLEEP_MASK_SPI); } -/* Extract R/W bit, register addresss, and data count from 4-byte header */ +/* Extract R/W bit, register address, and data count from 4-byte header */ static int header_says_to_read(uint8_t *data, uint32_t *reg, uint32_t *count) { uint32_t addr = data[1]; /* reg address is MSB first */ diff --git a/chip/g/usb.c b/chip/g/usb.c index 43f10f0968..0fc4f62242 100644 --- a/chip/g/usb.c +++ b/chip/g/usb.c @@ -907,7 +907,7 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in) /* * The Programmer's Guide says (p291) to stall any * further INs, but that's stupid because it'll destroy - * the packet we just tranferred to SPRAM, so don't do + * the packet we just transferred to SPRAM, so don't do * that (we tried it anyway, and Bad Things happened). * Also don't stop here, but keep looking at stuff. */ diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c index 97e886294b..1b1e0a80c6 100644 --- a/chip/lm4/gpio.c +++ b/chip/lm4/gpio.c @@ -83,7 +83,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal) void gpio_set_level(enum gpio_signal signal, int value) { /* - * Ok to write 0xff becuase LM4_GPIO_DATA bit-masks only the bit + * Ok to write 0xff because LM4_GPIO_DATA bit-masks only the bit * we care about. */ LM4_GPIO_DATA(gpio_list[signal].port, diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c index 0fcb411d23..1cb0bc4aaf 100644 --- a/chip/mec1322/clock.c +++ b/chip/mec1322/clock.c @@ -105,7 +105,7 @@ static void htimer_init(void) { MEC1322_INT_BLK_EN |= 1 << 17; MEC1322_INT_ENABLE(17) |= 1 << 20; /* GIRQ=17, aggregator bit = 20 */ - MEC1322_HTIMER_PRELOAD = 0; /* disable at begining */ + MEC1322_HTIMER_PRELOAD = 0; /* disable at beginning */ task_enable_irq(MEC1322_IRQ_HTIMER); } diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index 298a161762..3ce2717222 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -244,7 +244,7 @@ static void setup_lpc(void) /* Set up 8042 interface at 0x60/0x64 */ MEC1322_LPC_8042_BAR = 0x00608104; - /* Set up indication of Auxillary sts */ + /* Set up indication of Auxiliary sts */ MEC1322_8042_KB_CTRL |= 1 << 7; MEC1322_8042_ACT |= 1; @@ -630,7 +630,7 @@ static void lpc_clear_host_events(void) * the chipset_suspend is called. * * The chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON) - * is used to detect the S0ix transiton. + * is used to detect the S0ix transition. * * During S0ix entry, the wake mask for lid open is enabled. * diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c index 366f1624f4..ac5a301019 100644 --- a/chip/npcx/hwtimer.c +++ b/chip/npcx/hwtimer.c @@ -139,7 +139,7 @@ uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt) uint32_t sleep_time; uint16_t cnt = __hw_clock_event_count(); - /* Event has been triggered but timer ISR dosen't handle it */ + /* Event has been triggered but timer ISR doesn't handle it */ if (IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_TO_STS)) sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1) * evt_tick); /* Event hasn't been triggered */ diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c index 993b3565e4..d697c46045 100644 --- a/chip/npcx/i2c.c +++ b/chip/npcx/i2c.c @@ -38,7 +38,7 @@ */ #define I2C_MIN_TIMEOUT 25 -/* Marco functions of I2C */ +/* Macro functions of I2C */ #define I2C_START(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_START) #define I2C_STOP(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP) #define I2C_NACK(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK) @@ -66,7 +66,7 @@ enum smb_error { /* * Internal SMBus Interface driver states values, which reflect events - * which occured on the bus + * which occurred on the bus */ enum smb_oper_state_t { SMB_IDLE, diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index d893218640..8885013195 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -878,7 +878,7 @@ void lpc_lreset_pltrst_handler(void) pltrst_asserted ? "" : "de"); /* - * Once LRESET is de-asserted (low -> high), we need to intialize lpc + * Once LRESET is de-asserted (low -> high), we need to initialize lpc * settings once. If RSTCTL_LRESET_PLTRST_MODE is active, LPC registers * won't be reset by Host domain reset but Core domain does. */ diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c index fc6c11f334..cffae10fd9 100644 --- a/chip/stm32/adc-stm32f0.c +++ b/chip/stm32/adc-stm32f0.c @@ -169,7 +169,7 @@ static int adc_enable_watchdog_no_lock(void) (watchdog_ain_id << 26); adc_configure(watchdog_ain_id); - /* Clear AWD interupt flag */ + /* Clear AWD interrupt flag */ STM32_ADC_ISR = 0x80; /* Set Watchdog enable bit on a single channel */ STM32_ADC_CFGR1 |= STM32_ADC_CFGR1_AWDEN | STM32_ADC_CFGR1_AWDSGL; diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index a957686687..de92454369 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -165,7 +165,7 @@ void uart_interrupt(void) { #ifndef CONFIG_UART_TX_DMA /* - * When trasmission completes, enable sleep if we are done with Tx. + * When transmission completes, enable sleep if we are done with Tx. * After that, proceed if there is other interrupt to handle. */ if (STM32_USART_SR(UARTN_BASE) & STM32_USART_SR_TC) { diff --git a/chip/stm32/usart-stm32f0.c b/chip/stm32/usart-stm32f0.c index 4b24e49642..8ae2085498 100644 --- a/chip/stm32/usart-stm32f0.c +++ b/chip/stm32/usart-stm32f0.c @@ -46,7 +46,7 @@ static void usart_variant_disable(struct usart_config const *config) int index = config->hw->index; /* - * Only disable the shared interupt for USART3/4 if both USARTs are + * Only disable the shared interrupt for USART3/4 if both USARTs are * now disabled. */ if ((index == 0) || diff --git a/chip/stm32/usart_rx_dma.h b/chip/stm32/usart_rx_dma.h index 8056c2635e..a5a04e2829 100644 --- a/chip/stm32/usart_rx_dma.h +++ b/chip/stm32/usart_rx_dma.h @@ -38,7 +38,7 @@ * to use for the DMA circular buffer. This buffer must be large enough to * hide the worst case interrupt latency the system will encounter. The DMA * RX driver adds to the output of the usart_info command a high water mark - * of how many bytes were transfered out of this FIFO on any one interrupt. + * of how many bytes were transferred out of this FIFO on any one interrupt. * This value can be used to correctly size the FIFO by setting the FIFO_SIZE * to something large, stress test the USART, and run usart_info. After a * reasonable stress test the "DMA RX max_bytes" value will be a reasonable @@ -73,7 +73,7 @@ struct usart_rx_dma_state { size_t index; /* - * Maximum number of bytes transfered in any one RX interrupt. + * Maximum number of bytes transferred in any one RX interrupt. */ uint32_t max_bytes; }; @@ -94,7 +94,7 @@ struct usart_rx_dma { }; /* - * Function pointers needed to intialize a usart_rx struct. These shouldn't + * Function pointers needed to initialize a usart_rx struct. These shouldn't * be called in any other context as they assume that the producer or config * that they are passed was initialized with a complete usart_rx_dma struct. */ diff --git a/chip/stm32/usart_tx_dma.h b/chip/stm32/usart_tx_dma.h index 1dd3d7da41..33a97395ad 100644 --- a/chip/stm32/usart_tx_dma.h +++ b/chip/stm32/usart_tx_dma.h @@ -79,7 +79,7 @@ struct usart_tx_dma { }; /* - * Function pointers needed to intialize a usart_tx struct. These shouldn't + * Function pointers needed to initialize a usart_tx struct. These shouldn't * be called in any other context as they assume that the consumer or config * that they are passed was initialized with a complete usart_tx_dma struct. */ diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c index a3de00f53a..dbbc800ffe 100644 --- a/chip/stm32/usb.c +++ b/chip/stm32/usb.c @@ -326,7 +326,7 @@ void usb_init(void) /* Enable interrupt handlers */ task_enable_irq(STM32_IRQ_USB_LP); - /* set interrupts mask : reset/correct tranfer/errors */ + /* set interrupts mask : reset/correct transfer/errors */ STM32_USB_CNTR = 0xe400; #ifdef CONFIG_USB_SERIALNO |