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| author | Peter Marheine <pmarheine@chromium.org> | 2020-09-18 17:21:13 +1000 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-23 07:14:17 +0000 |
| commit | 3a2d3b3d140c07863f4dcb919f5d7b03505a50ed (patch) | |
| tree | d5c8815c870228a4c98814212630142dbea38a0e /chip | |
| parent | 614b68d763de108699185ca33abdf844dc5d7e0a (diff) | |
| download | chrome-ec-3a2d3b3d140c07863f4dcb919f5d7b03505a50ed.tar.gz | |
npcx7: set code RAM size to actual code RAM size
Munging the program flash size to account for the ROM header by default
also affects the assumed size of code RAM, which causes problems with
the MPU because it makes the code RAM region a weird size. Since we're
not using all of the code RAM space but it remains a full 256k in size,
explicitly set the code RAM size for the chips where we pretend program
memory is smaller than it actually is.
BUG=b:168732993
TEST=verified dalboz configures code RAM with size 256k
BRANCH=zork
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I0ab0954bc8a433d0d7c0c85945b012d45cc225ea
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2417788
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/npcx/config_chip-npcx7.h | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h index 35d57cca26..a6442e65fa 100644 --- a/chip/npcx/config_chip-npcx7.h +++ b/chip/npcx/config_chip-npcx7.h @@ -89,6 +89,13 @@ # define CONFIG_DATA_RAM_SIZE 0x00020000 #elif defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC) /* + * Code RAM is normally assumed to be same as image size, but since + * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we + * need to explicitly configure it. This is the actual size of code + * RAM on-chip. + */ +# define CONFIG_CODE_RAM_SIZE (256 * 1024) + /* * In npcx797wc and npcx797fc, the code RAM size is limited by the * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to * re-organize the memory to: @@ -103,17 +110,19 @@ * image size is a multiple of Flash erase granularity, we * sacrifice a whole sector. */ -# define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000) +# define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000) /* program memory base address for Code RAM (0x100B0000 - 256KB) */ # define CONFIG_PROGRAM_MEMORY_BASE 0x10070000 # define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */ /* 126 KB data RAM + 2 KB BT RAM size */ # define CONFIG_DATA_RAM_SIZE 0x00020000 - /* Override default NPCX_RAM_SIZE because we're excluding a block. */ + /* + * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE + * is not the actual size of code RAM. + */ # undef NPCX_RAM_SIZE -# define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + \ - NPCX_PROGRAM_MEMORY_SIZE + 0x1000) +# define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE) #else # error "Unsupported chip variant" #endif |