stm32: add embryonic support for STM32F76x

The STM32F76x is really close to the STM32F4 family, so the most concise
implementation is just using CHIP_FAMILY_STM32F4 and adding
CHIP_VARIANT_F76X.

Tune the clock settings to 180 Mhz CPU clock as the goal is performance.
(over-drive is not implemented yet to get to 216 Mhz)

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=ran on nucleo-f767zi board.
'make BOARD=nucleo-f767 flash', the red LED is on and the green LED
turns on/off when pressing the user button, UART console works properly.

Change-Id: I1f67df3aec874c965c81188df46c72de210728d9
Reviewed-on: https://chromium-review.googlesource.com/612750
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>

6 files changed, 134 insertions, 12 deletions

diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c
index 3c9f79f4c7..64f3d331e2 100644
--- a/chip/stm32/clock-stm32f4.c
+++ b/chip/stm32/clock-stm32f4.c
@@ -70,7 +70,7 @@ void config_hispeed_clock(void)
 #endif
 	int plldiv, pllinputclock;
 	int pllmult, vcoclock;
-	int systemdivq, systemclock;
+	int systemclock;
 	int usbdiv;
 	int i2sdiv;
 
@@ -95,8 +95,7 @@ void config_hispeed_clock(void)
 	vcoclock = pllinputclock * pllmult;
 
 	/* CPU/System clock */
-	systemclock = vcoclock / 4;
-	systemdivq = 1;
+	systemclock = vcoclock / STM32F4_PLLP_DIV;
 	/* USB clock = 48MHz exactly */
 	usbdiv = (vcoclock + (STM32F4_USB_REQ / 2)) / STM32F4_USB_REQ;
 	assert(vcoclock / usbdiv == STM32F4_USB_REQ);
@@ -147,7 +146,7 @@ void config_hispeed_clock(void)
 	STM32_RCC_PLLCFGR =
 		PLLCFGR_PLLM(plldiv) |
 		PLLCFGR_PLLN(pllmult) |
-		PLLCFGR_PLLP(systemdivq) |
+		PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) |
 #if defined(CONFIG_STM32_CLOCK_HSE_HZ)
 		PLLCFGR_PLLSRC_HSE |
 #else
diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h
new file mode 100644
index 0000000000..665bec36bf
--- /dev/null
+++ b/chip/stm32/config-stm32f76x.h
@@ -0,0 +1,60 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Memory mapping */
+#define CONFIG_FLASH_SIZE       (2048 * 1024)
+
+/* 3 regions type: 32K, 128K and 256K */
+#define SIZE_32KB (32 * 1024)
+#define SIZE_128KB (128 * 1024)
+#define SIZE_256KB (256 * 1024)
+#define CONFIG_FLASH_REGION_TYPE_COUNT 3
+#define CONFIG_FLASH_MULTIPLE_REGION \
+	(5 + (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB)
+
+/* Erasing 256K can take up to 2s, need to defer erase. */
+#define CONFIG_FLASH_DEFERRED_ERASE
+
+/* minimum write size for 3.3V. 1 for 1.8V */
+#define STM32_FLASH_WRITE_SIZE_1800 1
+#define STM32_FLASH_WS_DIV_1800 16000000
+#define STM32_FLASH_WRITE_SIZE_3300 4
+#define STM32_FLASH_WS_DIV_3300 30000000
+
+/* No page mode on STM32F, so no benefit to larger write sizes */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
+
+/* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF*/
+/* SRAM1:    368kB 0x20020000 - 0x2007BFFF */
+/* SRAM2:     16kB 0x2007C000 - 0x2007FFFF */
+#define CONFIG_RAM_BASE		0x20000000
+#define CONFIG_RAM_SIZE		0x00080000
+
+#define CONFIG_RO_MEM_OFF	0
+#define CONFIG_RO_SIZE		(1024 * 1024)
+#define CONFIG_RW_MEM_OFF	(1024 * 1024)
+#define CONFIG_RW_SIZE		(1024 * 1024)
+
+#define CONFIG_RO_STORAGE_OFF	0
+#define CONFIG_RW_STORAGE_OFF	0
+
+#define CONFIG_EC_PROTECTED_STORAGE_OFF		0
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE	CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_OFF		CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE					\
+		 (CONFIG_FLASH_SIZE - CONFIG_EC_WRITABLE_STORAGE_OFF)
+
+#define CONFIG_WP_STORAGE_OFF		CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE		CONFIG_EC_PROTECTED_STORAGE_SIZE
+
+#undef I2C_PORT_COUNT
+#define I2C_PORT_COUNT	4
+
+/* Use PSTATE embedded in the RO image, not in its own erase block */
+#define CONFIG_FLASH_PSTATE
+#undef CONFIG_FLASH_PSTATE_BANK
+
+/* Number of IRQ vectors on the NVIC */
+#define CONFIG_IRQ_COUNT	109
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index ca93e8f80a..fc8174bc47 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -38,6 +38,8 @@
 #include "config-stm32l100.h"
 #elif defined(CHIP_VARIANT_STM32L442)
 #include "config-stm32l442.h"
+#elif defined(CHIP_VARIANT_STM32F76X)
+#include "config-stm32f76x.h"
 #elif defined(CHIP_FAMILY_STM32F4)
 /* STM32F4 family */
 #include "config-stm32f446.h"
diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c
index 6fe7df91c5..843bbf48e4 100644
--- a/chip/stm32/flash-stm32f3.c
+++ b/chip/stm32/flash-stm32f3.c
@@ -12,9 +12,36 @@
 #include "system.h"
 #include "panic.h"
 
-#ifdef CHIP_FAMILY_STM32F4
 /*****************************************************************************/
 /* Physical layer APIs */
+#ifdef CHIP_VARIANT_STM32F76X
+/*
+ * 8 "erase" sectors : 32KB/32KB/32KB/32KB/128KB/256KB/256KB/256KB
+ */
+struct ec_flash_bank const flash_bank_array[] = {
+	{
+		.count = 4,
+		.size_exp = __fls(SIZE_32KB),
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.erase_size_exp = __fls(SIZE_32KB),
+		.protect_size_exp = __fls(SIZE_32KB),
+	},
+	{
+		.count = 1,
+		.size_exp = __fls(SIZE_128KB),
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.erase_size_exp = __fls(SIZE_128KB),
+		.protect_size_exp = __fls(SIZE_128KB),
+	},
+	{
+		.count = (CONFIG_FLASH_SIZE - SIZE_256KB) / SIZE_256KB,
+		.write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE),
+		.size_exp = __fls(SIZE_256KB),
+		.erase_size_exp = __fls(SIZE_256KB),
+		.protect_size_exp = __fls(SIZE_256KB),
+	},
+};
+#elif defined(CHIP_FAMILY_STM32F4)
 /*
  * 8 "erase" sectors : 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB
  */
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 918afaf974..bfe5b7321c 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -213,7 +213,7 @@
 #define STM32_USART_REG(base, offset) REG32((base) + (offset))
 
 #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \
-	defined(CHIP_FAMILY_STM32L4)
+	defined(CHIP_FAMILY_STM32L4) || defined(CHIP_VARIANT_STM32F76X)
 #define STM32_USART_CR1(base)      STM32_USART_REG(base, 0x00)
 #define STM32_USART_CR1_UE		(1 << 0)
 #define STM32_USART_CR1_UESM            (1 << 1)
@@ -417,6 +417,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define GPIO_ALT_TIM9_11             0x3
 #define GPIO_ALT_I2C                 0x4
 #define GPIO_ALT_SPI                 0x5
+#define GPIO_ALT_SPI3                0x6
 #define GPIO_ALT_USART               0x7
 #define GPIO_ALT_I2C_23              0x9
 #define GPIO_ALT_USB                 0xA
@@ -962,6 +963,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32F4_HSI_CLOCK 16000000
 #define STM32F4_LSI_CLOCK 32000
 #define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK
+#define STM32F4_PLLP_DIV 4
 #define STM32F4_AHB_PRE 0x8
 #define STM32F4_APB1_PRE 0x0
 #define STM32F4_APB2_PRE 0x0
@@ -977,6 +979,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32F4_HSI_CLOCK 16000000
 #define STM32F4_LSI_CLOCK 32000
 #define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
+#define STM32F4_PLLP_DIV 4
 #define STM32F4_AHB_PRE 0x0
 #define STM32F4_APB1_PRE 0x4
 #define STM32F4_APB2_PRE 0x4
@@ -992,11 +995,28 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32F4_HSI_CLOCK 16000000
 #define STM32F4_LSI_CLOCK 32000
 #define STM32F4_TIMER_CLOCK STM32F4_IO_CLOCK
+#define STM32F4_PLLP_DIV 4
 #define STM32F4_AHB_PRE 0x8
 #define STM32F4_APB1_PRE 0x0
 #define STM32F4_APB2_PRE 0x0
 #define STM32_FLASH_ACR_LATENCY     (1 << 0)
 
+#elif defined(CHIP_VARIANT_STM32F76X)
+/* Required or recommended clocks for stm32f767/769 */
+#define STM32F4_PLL_REQ 2000000
+#define STM32F4_RTC_REQ 1000000
+#define STM32F4_IO_CLOCK 45000000
+#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */
+#define STM32F4_VCO_CLOCK 360000000
+#define STM32F4_HSI_CLOCK 16000000
+#define STM32F4_LSI_CLOCK 32000
+#define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2)
+#define STM32F4_PLLP_DIV 2   /* sys = VCO/2  = 180 Mhz */
+#define STM32F4_AHB_PRE 0x0  /* AHB = sysclk = 180 Mhz */
+#define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */
+#define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */
+#define STM32_FLASH_ACR_LATENCY     (5 << 0)
+
 #else
 #error "No valid clocks defined"
 #endif
@@ -1214,7 +1234,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 /* --- SPI --- */
 #define STM32_SPI1_BASE             0x40013000
 #define STM32_SPI2_BASE             0x40003800
-#define STM32_SPI3_BASE             0x40003c00 /* STM32F373 and STM32L4 */
+#define STM32_SPI3_BASE             0x40003c00 /* STM32F373, STM32L4, STM32F7 */
 
 /* The SPI controller registers */
 struct stm32_spi_regs {
@@ -1872,7 +1892,7 @@ enum dma_channel {
 	/* Legacy naming for uart.c */
 	STM32_DMAC_USART1_TX = STM32_DMAS_USART1_TX,
 	STM32_DMAC_USART1_RX = STM32_DMAS_USART1_RX,
-#if defined(CHIP_VARIANT_STM32F411)
+#if defined(CHIP_VARIANT_STM32F411) || defined(CHIP_VARIANT_STM32F76X)
 	STM32_DMAS_USART2_TX = STM32_DMA1_STREAM6,
 	STM32_DMAS_USART2_RX = STM32_DMA1_STREAM5,
 
@@ -1881,7 +1901,7 @@ enum dma_channel {
 	STM32_DMAC_USART2_RX = STM32_DMAS_USART2_RX,
 #endif
 
-#if defined(CHIP_VARIANT_STM32F411)
+#if defined(CHIP_VARIANT_STM32F411) || defined(CHIP_VARIANT_STM32F76X)
 	STM32_DMAC_I2C1_TX = STM32_DMA1_STREAM1,
 	STM32_DMAC_I2C1_RX = STM32_DMA1_STREAM0,
 
@@ -1909,6 +1929,8 @@ enum dma_channel {
 	STM32_DMAC_SPI1_RX = STM32_DMA2_STREAM0, /* REQ 3 */
 	STM32_DMAC_SPI2_TX = STM32_DMA1_STREAM4, /* REQ 0 */
 	STM32_DMAC_SPI2_RX = STM32_DMA1_STREAM3, /* REQ 0 */
+	STM32_DMAC_SPI3_TX = STM32_DMA1_STREAM7, /* REQ 0 */
+	STM32_DMAC_SPI3_RX = STM32_DMA1_STREAM0, /* REQ 0 */
 
 };
 
@@ -1934,6 +1956,8 @@ enum dma_channel {
 #define STM32_SPI1_RX_REQ_CH 3
 #define STM32_SPI2_TX_REQ_CH 0
 #define STM32_SPI2_RX_REQ_CH 0
+#define STM32_SPI3_TX_REQ_CH 0
+#define STM32_SPI3_RX_REQ_CH 0
 
 #define STM32_DMAS_TOTAL_COUNT 16
 
diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c
index 353dac3085..c0697be736 100644
--- a/chip/stm32/spi_master.c
+++ b/chip/stm32/spi_master.c
@@ -16,13 +16,21 @@
 #include "timer.h"
 #include "util.h"
 
+#if defined(CHIP_VARIANT_STM32F373)  || \
+	defined(CHIP_FAMILY_STM32L4) || \
+	defined(CHIP_VARIANT_STM32F76X)
+#define HAS_SPI3
+#else
+#undef  HAS_SPI3
+#endif
+
 /* The second (and third if available) SPI port are used as master */
 static stm32_spi_regs_t *SPI_REGS[] = {
 #ifdef CONFIG_STM32_SPI1_MASTER
 	STM32_SPI1_REGS,
 #endif
 	STM32_SPI2_REGS,
-#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4)
+#ifdef HAS_SPI3
 	STM32_SPI3_REGS,
 #endif
 };
@@ -62,10 +70,11 @@ static const struct dma_option dma_tx_option[] = {
 		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 		| F4_CHANNEL(STM32_SPI2_TX_REQ_CH)
 	},
-#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4)
+#ifdef HAS_SPI3
 	{
 		STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr,
 		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
+		| F4_CHANNEL(STM32_SPI3_TX_REQ_CH)
 	},
 #endif
 };
@@ -83,10 +92,11 @@ static const struct dma_option dma_rx_option[] = {
 		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 		| F4_CHANNEL(STM32_SPI2_RX_REQ_CH)
 	},
-#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4)
+#ifdef HAS_SPI3
 	{
 		STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr,
 		STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
+		| F4_CHANNEL(STM32_SPI3_RX_REQ_CH)
 	},
 #endif
 };