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| author | Dino Li <Dino.Li@ite.com.tw> | 2021-08-31 13:51:43 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-09-01 21:05:31 +0000 |
| commit | 14b2c5df42665b8d592807de604ec7a930ead262 (patch) | |
| tree | 7672256af06d2536bbf35dba5165a615a01f97d9 /chip | |
| parent | 4e6e68a2f29fae523d2f2e9e92afe3174c1c54c9 (diff) | |
| download | chrome-ec-14b2c5df42665b8d592807de604ec7a930ead262.tar.gz | |
it83xx/irq: there is no need to configure IER on nds32 core chip
Configure interrupt enable register is redundant on nds32 core chip
(IT8320). We just need to configure extended IER.
BRANCH=asurada, dedede
BUG=b:197308582
TEST=buildall passes, storo and hayato boot.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I8f99f7b937ac98d95b2f50f5be7b461ae3e9a413
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3134888
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/it83xx/irq.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c index 945f1909de..c2564c05a3 100644 --- a/chip/it83xx/irq.c +++ b/chip/it83xx/irq.c @@ -107,7 +107,11 @@ void chip_enable_irq(int irq) int group = irq / 8; int bit = irq % 8; - IT83XX_INTC_REG(irq_groups[group].ier_off) |= BIT(bit); + /* SOC's interrupts share CPU machine-mode external interrupt */ + if (IS_ENABLED(CHIP_CORE_RISCV)) + IT83XX_INTC_REG(irq_groups[group].ier_off) |= BIT(bit); + + /* SOC's interrupts use CPU HW interrupt 2 ~ 15 */ if (IS_ENABLED(CHIP_CORE_NDS32)) IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) |= BIT(bit); } @@ -117,7 +121,11 @@ void chip_disable_irq(int irq) int group = irq / 8; int bit = irq % 8; - IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit); + /* SOC's interrupts share CPU machine-mode external interrupt */ + if (IS_ENABLED(CHIP_CORE_RISCV)) + IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit); + + /* SOC's interrupts use CPU HW interrupt 2 ~ 15 */ if (IS_ENABLED(CHIP_CORE_NDS32)) IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) &= ~BIT(bit); } |