diff options
| author | Josie Nordrum <JosieNordrum@google.com> | 2022-05-19 15:38:51 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-09-06 19:10:05 +0000 |
| commit | 912d6736d5cbf18c9087a5df55526b38ddf2096e (patch) | |
| tree | b9bce093f98ee59bb60e1adf23ed29a1591751c8 /chip | |
| parent | 6493af0aeb66c95fb3204ae68b46aa62ec85262f (diff) | |
| download | chrome-ec-912d6736d5cbf18c9087a5df55526b38ddf2096e.tar.gz | |
stm32f0.h: update number of channels per controller
Define only channels valid for each chip. Remove reference to channel 7
when setting callbacks for DMA channels 4+.
BRANCH=None
BUG=b:233240524
TEST=make buildall -j
Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I0258498cc075817b7ee59963482bc6a391853a90
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3656369
Reviewed-by: Bobby Casey <bobbycasey@google.com>
Commit-Queue: Josie Nordrum <josienordrum@google.com>
Reviewed-by: Craig Hesling <hesling@chromium.org>
Tested-by: Josie Nordrum <josienordrum@google.com>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/dma.c | 4 | ||||
| -rw-r--r-- | chip/stm32/registers-stm32f0.h | 15 |
2 files changed, 10 insertions, 9 deletions
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index a36e015ce9..a7536fe29a 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -360,9 +360,7 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_2_3, dma_event_interrupt_channel_2_3, 1); static void dma_event_interrupt_channel_4_7(void) { int i; - const unsigned int max_chan = MIN(STM32_DMAC_CH7, STM32_DMAC_COUNT); - - for (i = STM32_DMAC_CH4; i <= max_chan; i++) { + for (i = STM32_DMAC_CH4; i < STM32_DMAC_COUNT; i++) { if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(i)) { dma_clear_isr(i); if (dma_irq[i].cb != NULL) diff --git a/chip/stm32/registers-stm32f0.h b/chip/stm32/registers-stm32f0.h index 867c1cc909..f81b663284 100644 --- a/chip/stm32/registers-stm32f0.h +++ b/chip/stm32/registers-stm32f0.h @@ -675,19 +675,19 @@ enum dma_channel { STM32_DMAC_CH3 = 2, STM32_DMAC_CH4 = 3, STM32_DMAC_CH5 = 4, +#if defined(CHIP_VARIANT_STM32F07X) || defined(CHIP_VARIANT_STM32F09X) STM32_DMAC_CH6 = 5, STM32_DMAC_CH7 = 6, - /* - * Skip CH8, it should belong to DMA engine 1. - * Sharing code with STM32s that have 16 engines will be easier. - */ +#endif +/* STM32F09 has two DMAs with 7 & 5 channels, respectively */ +#ifdef CHIP_VARIANT_STM32F09X STM32_DMAC_CH9 = 8, STM32_DMAC_CH10 = 9, STM32_DMAC_CH11 = 10, STM32_DMAC_CH12 = 11, STM32_DMAC_CH13 = 12, STM32_DMAC_CH14 = 13, - +#endif /* Channel functions */ STM32_DMAC_ADC = STM32_DMAC_CH1, STM32_DMAC_SPI1_RX = STM32_DMAC_CH2, @@ -715,7 +715,10 @@ enum dma_channel { STM32_DMAC_COUNT = 5, #endif }; - +/* + * TODO(b/233369173): This file was originally shared by many MCUs, + * 8 is assumed to be the max number of channels for all chips. + */ #define STM32_DMAC_PER_CTLR 8 /* Registers for a single channel of the DMA controller */ |