diff options
| author | Keith Short <keithshort@chromium.org> | 2021-08-03 11:58:05 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-03 21:42:19 +0000 |
| commit | 34eabe36d503fc9a3128c3710a19cee8ee5df0bd (patch) | |
| tree | 9e92e47dc2f0dcb9759cd6f509cbf8a462867923 /chip | |
| parent | fe82812283a6a4001bddc5aeea9e6b4f184cd17a (diff) | |
| download | chrome-ec-34eabe36d503fc9a3128c3710a19cee8ee5df0bd.tar.gz | |
COIL: Change host interface option to CONFIG_HOSTCMD_SHI
Update SPI host interface config option for inclusive language.
BUG=b:163885307
BRANCH=none
TEST=compare_build.sh
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I808d5960fa3e746626465bedc626a95e0f0aaa3f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066271
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/npcx/build.mk | 2 | ||||
| -rw-r--r-- | chip/npcx/gpio-npcx5.c | 2 | ||||
| -rw-r--r-- | chip/npcx/gpio-npcx9.c | 2 | ||||
| -rw-r--r-- | chip/npcx/gpio.c | 2 | ||||
| -rw-r--r-- | chip/npcx/shi_chip.h | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index a013ef5ef5..4be1b2994f 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -32,7 +32,7 @@ chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o chip-$(CONFIG_HOSTCMD_X86)+=lpc.o chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o chip-$(CONFIG_PECI)+=peci.o -chip-$(CONFIG_HOSTCMD_SPS)+=shi.o +chip-$(CONFIG_HOSTCMD_SHI)+=shi.o chip-$(CONFIG_CEC)+=cec.o # pwm functions are implemented with the fan functions chip-$(CONFIG_PWM)+=pwm.o diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c index d6a28300ba..e1d13c98d1 100644 --- a/chip/npcx/gpio-npcx5.c +++ b/chip/npcx/gpio-npcx5.c @@ -179,7 +179,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); -#ifdef CONFIG_HOSTCMD_SPS +#ifdef CONFIG_HOSTCMD_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c index 441924d89e..2bb4ae085c 100644 --- a/chip/npcx/gpio-npcx9.c +++ b/chip/npcx/gpio-npcx9.c @@ -196,7 +196,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); -#ifdef CONFIG_HOSTCMD_SPS +#ifdef CONFIG_HOSTCMD_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index fece08c0f4..e740f0aa9f 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -560,7 +560,7 @@ void gpio_pre_init(void) #endif /* Pin_Mux for LPC & SHI */ -#ifdef CONFIG_HOSTCMD_SPS +#ifdef CONFIG_HOSTCMD_SHI /* Switching to eSPI mode for SHI interface */ NPCX_DEVCNT |= 0x08; /* Alternate Intel bus interface LPC/eSPI to GPIOs first */ diff --git a/chip/npcx/shi_chip.h b/chip/npcx/shi_chip.h index f701067715..c14aec196e 100644 --- a/chip/npcx/shi_chip.h +++ b/chip/npcx/shi_chip.h @@ -8,7 +8,7 @@ #ifndef SHI_CHIP_H_ #define SHI_CHIP_H_ -#ifdef CONFIG_HOSTCMD_SPS +#ifdef CONFIG_HOSTCMD_SHI /** * Called when the NSS level changes, signalling the start of a SHI * transaction. |