diff options
author | Wealian Liao <whliao@nuvoton.corp-partner.google.com> | 2021-07-27 16:03:06 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-07-28 04:44:29 +0000 |
commit | 441c185367ecf4673bc3a290c976398a48878e49 (patch) | |
tree | 4c7362ccbf0f5085bd8d7b067966d7f488fb526d /chip | |
parent | 63f9b88896d56d049a0ddec91951f6c76d1a2f3a (diff) | |
download | chrome-ec-441c185367ecf4673bc3a290c976398a48878e49.tar.gz |
npcx: Add alternate function option for PS2_2 & PS2_3
NPCX alternate switch function uses the GPIO number to select which
register should be set. Currently, we have a scenario to enable
CONFIG_PS2 & use ADC5(GPIO37) or ADC6(GPIO34) with NPCX9. The
CONFIG_PS2 condition hides the alternate table for ADC5/6. It makes
GPIO37 & GPIO34 are both set to PS2 function.
This CL adds NPCX_PS2_MODULE_2 & NPCX_PS2_MODULE_3 options to assign
PS2 function for alternate pin explicitly.
BUG=none
BRANCH=none
TEST=make buildall
TEST=Enable CONFIG_PS2 & check ADC5/6 functionality.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Id02fb8ecfd488db133351119be84c357dc18da15
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058151
Reviewed-by: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/npcx/config_chip-npcx5.h | 6 | ||||
-rw-r--r-- | chip/npcx/config_chip-npcx7.h | 7 | ||||
-rw-r--r-- | chip/npcx/config_chip-npcx9.h | 7 | ||||
-rw-r--r-- | chip/npcx/gpio_chip-npcx5.h | 6 | ||||
-rw-r--r-- | chip/npcx/gpio_chip-npcx7.h | 6 | ||||
-rw-r--r-- | chip/npcx/gpio_chip-npcx9.h | 8 |
6 files changed, 34 insertions, 6 deletions
diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h index 331b5e5474..434caba1d8 100644 --- a/chip/npcx/config_chip-npcx5.h +++ b/chip/npcx/config_chip-npcx5.h @@ -26,6 +26,12 @@ #define UART_MODULE_COUNT 1 /* + * For NPCX5, PS2_3 pins also support other alternate functions (e.g., TA2). + * PS2_3 should be Explicit defined. + */ +#undef NPCX_PS2_MODULE_3 + +/* * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one * additional port. */ diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h index 5919f69af8..434c3a7889 100644 --- a/chip/npcx/config_chip-npcx7.h +++ b/chip/npcx/config_chip-npcx7.h @@ -43,6 +43,13 @@ #define NPCX_SECOND_UART #define UART_MODULE_COUNT 2 +/* + * For NPCX7, PS2_2 & PS2_3 pins also support other alternate functions + * (e.g., ADC5, ADC6, TA2). PS2_2 & PS2_3 should be Explicit defined. + */ +#undef NPCX_PS2_MODULE_2 +#undef NPCX_PS2_MODULE_3 + /* 64-bit timer support */ #define NPCX_ITIM64_SUPPORT #else diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h index da17cc76ae..0248c40f86 100644 --- a/chip/npcx/config_chip-npcx9.h +++ b/chip/npcx/config_chip-npcx9.h @@ -33,6 +33,13 @@ #define UART_MODULE_COUNT 2 /* + * For NPCX9, PS2_2 & PS2_3 pins also support other alternate functions + * (e.g., ADC5, ADC6, TA2). PS2_2 & PS2_3 should be Explicit defined. + */ +#undef NPCX_PS2_MODULE_2 +#undef NPCX_PS2_MODULE_3 + +/* * Number of I2C controllers. Controller 5/6 has 2 ports, so the chip has * two additional ports. */ diff --git a/chip/npcx/gpio_chip-npcx5.h b/chip/npcx/gpio_chip-npcx5.h index ee113aea44..83916a421b 100644 --- a/chip/npcx/gpio_chip-npcx5.h +++ b/chip/npcx/gpio_chip-npcx5.h @@ -206,7 +206,7 @@ /* MFT Module */ #define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */ -#ifdef CONFIG_PS2 +#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3) #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */ #else #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */ @@ -255,7 +255,11 @@ #define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */ #define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */ #define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */ +#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3) #define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */ +#else +#define NPCX_ALT_GPIO_A_7 +#endif #define NPCX_ALT_TABLE { \ NPCX_ALT_GPIO_0_3 /* KSO16 */ \ diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h index 2f6337d896..7f815e6d30 100644 --- a/chip/npcx/gpio_chip-npcx7.h +++ b/chip/npcx/gpio_chip-npcx7.h @@ -230,7 +230,7 @@ #define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2 */ #define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3 */ #define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4 */ -#ifdef CONFIG_PS2 +#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_2) #define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */ #define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */ #else @@ -264,7 +264,7 @@ #define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */ #define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */ #define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */ -#ifdef CONFIG_PS2 +#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3) #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */ #else #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */ @@ -346,7 +346,7 @@ #define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */ #define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */ -#ifdef CONFIG_PS2 +#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3) #define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */ #else #define NPCX_ALT_GPIO_A_7 diff --git a/chip/npcx/gpio_chip-npcx9.h b/chip/npcx/gpio_chip-npcx9.h index f07618317c..005a03d83e 100644 --- a/chip/npcx/gpio_chip-npcx9.h +++ b/chip/npcx/gpio_chip-npcx9.h @@ -212,7 +212,7 @@ #define NPCX_ALT_GPIO_4_3 ALT(4, 3, NPCX_ALT(6, ADC2_SL)) /* ADC2 */ #define NPCX_ALT_GPIO_4_2 ALT(4, 2, NPCX_ALT(6, ADC3_SL)) /* ADC3 */ #define NPCX_ALT_GPIO_4_1 ALT(4, 1, NPCX_ALT(6, ADC4_SL)) /* ADC4 */ -#ifdef CONFIG_PS2 +#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_2) #define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(3, PS2_2_SL)) /* PS2_CLK2 */ #define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(3, PS2_2_SL)) /* PS2_DATA2 */ #else @@ -230,7 +230,11 @@ #define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */ #define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */ #define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */ +#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3) #define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */ +#else +#define NPCX_ALT_GPIO_A_7 +#endif /* UART Module */ #define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 */ @@ -253,7 +257,7 @@ #define NPCX_ALT_GPIO_4_0 ALT(4, 0, NPCX_ALT(3, TA1_SL1)) /* TA1_SEL1 */ #define NPCX_ALT_GPIO_7_3 ALT(7, 3, NPCX_ALT(3, TA2_SL1)) /* TA2_SEL1 */ #define NPCX_ALT_GPIO_9_3 ALT(9, 3, NPCX_ALT(C, TA1_SL2)) /* TA1_SEL2 */ -#ifdef CONFIG_PS2 +#if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3) #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, PS2_3_SL2)) /* PS2_CLK3 */ #else #define NPCX_ALT_GPIO_A_6 ALT(A, 6, NPCX_ALT(C, TA2_SL2)) /* TA2_SEL2 */ |