Remove _OFF from GPIO register macros

This is left over from when we had a pair of macros for each GPIO
register, one which concatenated its base address name and one which
took a base address.  Only the latter has survived, but its naming is
longer than it needs to be and isn't consistent with other register
banks (USART, TIM, etc.).

No code changes, just renaming macros.

BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms

Change-Id: I15a282fd01db2a25219970e28ce551d8dc80193f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48226
Reviewed-by: Bill Richardson <wfrichar@chromium.org>

5 files changed, 40 insertions, 40 deletions

diff --git a/chip/stm32/gpio-stm32f100.c b/chip/stm32/gpio-stm32f100.c
index 5e55ca8834..9ce1ab110a 100644
--- a/chip/stm32/gpio-stm32f100.c
+++ b/chip/stm32/gpio-stm32f100.c
@@ -80,7 +80,7 @@ void gpio_set_flags(enum gpio_signal signal, int flags)
 		 */
 		if (flags & GPIO_PULL_UP) {
 			mask |= 0x88888888 & cnf;
-			STM32_GPIO_BSRR_OFF(g->port) |= g->mask;
+			STM32_GPIO_BSRR(g->port) |= g->mask;
 			gpio_set_level(signal, 1);
 		} else if (flags & GPIO_PULL_DOWN) {
 			mask |= 0x88888888 & cnf;
@@ -165,20 +165,20 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
 uint16_t *gpio_get_level_reg(enum gpio_signal signal, uint32_t *mask)
 {
 	*mask = gpio_list[signal].mask;
-	return (uint16_t *)&STM32_GPIO_IDR_OFF(gpio_list[signal].port);
+	return (uint16_t *)&STM32_GPIO_IDR(gpio_list[signal].port);
 }
 
 
 int gpio_get_level(enum gpio_signal signal)
 {
-	return !!(STM32_GPIO_IDR_OFF(gpio_list[signal].port) &
+	return !!(STM32_GPIO_IDR(gpio_list[signal].port) &
 		  gpio_list[signal].mask);
 }
 
 
 void gpio_set_level(enum gpio_signal signal, int value)
 {
-	STM32_GPIO_BSRR_OFF(gpio_list[signal].port) =
+	STM32_GPIO_BSRR(gpio_list[signal].port) =
 			gpio_list[signal].mask << (value ? 0 : 16);
 }
 
diff --git a/chip/stm32/gpio-stm32l15x.c b/chip/stm32/gpio-stm32l15x.c
index 6d61d05fa2..70cdec0b31 100644
--- a/chip/stm32/gpio-stm32l15x.c
+++ b/chip/stm32/gpio-stm32l15x.c
@@ -29,21 +29,21 @@ void gpio_set_flags(enum gpio_signal signal, int flags)
 	uint32_t val;
 
 	/* Set up pullup / pulldown */
-	val = STM32_GPIO_PUPDR_OFF(g->port) & ~mask2;
+	val = STM32_GPIO_PUPDR(g->port) & ~mask2;
 	if (flags & GPIO_PULL_UP)
 		val |= 0x55555555 & mask2;	/* Pull Up = 01 */
 	else if (flags & GPIO_PULL_DOWN)
 		val |= 0xaaaaaaaa & mask2;	/* Pull Down = 10 */
-	STM32_GPIO_PUPDR_OFF(g->port) = val;
+	STM32_GPIO_PUPDR(g->port) = val;
 
 	/*
 	 * Select open drain first, so that we don't glitch the signal when
 	 * changing the line to an output.
 	 */
 	if (flags & GPIO_OPEN_DRAIN)
-		STM32_GPIO_OTYPER_OFF(g->port) |= g->mask;
+		STM32_GPIO_OTYPER(g->port) |= g->mask;
 
-	val = STM32_GPIO_MODER_OFF(g->port) & ~mask2;
+	val = STM32_GPIO_MODER(g->port) & ~mask2;
 	if (flags & GPIO_OUTPUT) {
 		/*
 		 * Set pin level first to avoid glitching.  This is harmless on
@@ -57,11 +57,11 @@ void gpio_set_flags(enum gpio_signal signal, int flags)
 
 		/* General purpose, MODE = 01 */
 		val |= 0x55555555 & mask2;
-		STM32_GPIO_MODER_OFF(g->port) = val;
+		STM32_GPIO_MODER(g->port) = val;
 
 	} else if (flags & GPIO_INPUT) {
 		/* Input, MODE=00 */
-		STM32_GPIO_MODER_OFF(g->port) = val;
+		STM32_GPIO_MODER(g->port) = val;
 	}
 
 	/* Set up interrupts if necessary */
@@ -131,7 +131,7 @@ void gpio_set_alternate_function(int port, int mask, int func)
 	int bit;
 	uint8_t half;
 	uint32_t afr;
-	uint32_t moder = STM32_GPIO_MODER_OFF(port);
+	uint32_t moder = STM32_GPIO_MODER(port);
 
 	if (func < 0) {
 		/* Return to normal GPIO function, defaulting to input. */
@@ -140,13 +140,13 @@ void gpio_set_alternate_function(int port, int mask, int func)
 			moder &= ~(0x3 << (bit * 2 + 16));
 			mask &= ~(1 << bit);
 		}
-		STM32_GPIO_MODER_OFF(port) = moder;
+		STM32_GPIO_MODER(port) = moder;
 		return;
 	}
 
 	/* Low half of the GPIO bank */
 	half = mask & 0xff;
-	afr = STM32_GPIO_AFRL_OFF(port);
+	afr = STM32_GPIO_AFRL(port);
 	while (half) {
 		bit = 31 - __builtin_clz(half);
 		afr &= ~(0xf << (bit * 4));
@@ -155,11 +155,11 @@ void gpio_set_alternate_function(int port, int mask, int func)
 		moder |= 0x2 << (bit * 2 + 0);
 		half &= ~(1 << bit);
 	}
-	STM32_GPIO_AFRL_OFF(port) = afr;
+	STM32_GPIO_AFRL(port) = afr;
 
 	/* High half of the GPIO bank */
 	half = mask >> 8;
-	afr = STM32_GPIO_AFRH_OFF(port);
+	afr = STM32_GPIO_AFRH(port);
 	while (half) {
 		bit = 31 - __builtin_clz(half);
 		afr &= ~(0xf << (bit * 4));
@@ -168,19 +168,19 @@ void gpio_set_alternate_function(int port, int mask, int func)
 		moder |= 0x2 << (bit * 2 + 16);
 		half &= ~(1 << bit);
 	}
-	STM32_GPIO_AFRH_OFF(port) = afr;
-	STM32_GPIO_MODER_OFF(port) = moder;
+	STM32_GPIO_AFRH(port) = afr;
+	STM32_GPIO_MODER(port) = moder;
 }
 
 int gpio_get_level(enum gpio_signal signal)
 {
-	return !!(STM32_GPIO_IDR_OFF(gpio_list[signal].port) &
+	return !!(STM32_GPIO_IDR(gpio_list[signal].port) &
 		  gpio_list[signal].mask);
 }
 
 void gpio_set_level(enum gpio_signal signal, int value)
 {
-	STM32_GPIO_BSRR_OFF(gpio_list[signal].port) =
+	STM32_GPIO_BSRR(gpio_list[signal].port) =
 			gpio_list[signal].mask << (value ? 0 : 16);
 }
 
diff --git a/chip/stm32/keyboard_raw.c b/chip/stm32/keyboard_raw.c
index 4bc516f289..bc810e2a04 100644
--- a/chip/stm32/keyboard_raw.c
+++ b/chip/stm32/keyboard_raw.c
@@ -87,7 +87,7 @@ test_mockable void keyboard_raw_drive_column(int out)
 		}
 
 		if (bsrr)
-			STM32_GPIO_BSRR_OFF(kb_out_ports[i]) = bsrr;
+			STM32_GPIO_BSRR(kb_out_ports[i]) = bsrr;
 
 		if (done)
 			break;
@@ -104,7 +104,7 @@ test_mockable int keyboard_raw_read_rows(void)
 	for (i = 0; i < KEYBOARD_ROWS; i++) {
 		port = gpio_list[GPIO_KB_IN00 + i].port;
 		if (port != prev_port) {
-			port_val = STM32_GPIO_IDR_OFF(port);
+			port_val = STM32_GPIO_IDR(port);
 			prev_port = port;
 		}
 
diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c
index 13568a254b..bad0c23d17 100644
--- a/chip/stm32/power_led.c
+++ b/chip/stm32/power_led.c
@@ -43,9 +43,9 @@ static void power_led_use_pwm(void)
 	uint32_t val;
 
 	/* Configure power LED GPIO for TIM2/PWM alternate function */
-	val = STM32_GPIO_CRL_OFF(GPIO_B) & ~0x0000f000;
+	val = STM32_GPIO_CRL(GPIO_B) & ~0x0000f000;
 	val |= 0x00009000;	/* alt. function (TIM2/PWM) */
-	STM32_GPIO_CRL_OFF(GPIO_B) = val;
+	STM32_GPIO_CRL(GPIO_B) = val;
 
 	/* Enable TIM2 clock */
 	STM32_RCC_APB1ENR |= 0x1;
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index c8f1fe0a5a..ea97318606 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -183,16 +183,16 @@
 #define STM32_GPIOE_BASE            0x40021000
 #define STM32_GPIOH_BASE            0x40021400
 
-#define STM32_GPIO_MODER_OFF(b)     REG32((b) + 0x00)
-#define STM32_GPIO_OTYPER_OFF(b)    REG16((b) + 0x04)
-#define STM32_GPIO_OSPEEDR_OFF(b)   REG32((b) + 0x08)
-#define STM32_GPIO_PUPDR_OFF(b)     REG32((b) + 0x0C)
-#define STM32_GPIO_IDR_OFF(b)       REG16((b) + 0x10)
-#define STM32_GPIO_ODR_OFF(b)       REG16((b) + 0x14)
-#define STM32_GPIO_BSRR_OFF(b)      REG32((b) + 0x18)
-#define STM32_GPIO_LCKR_OFF(b)      REG32((b) + 0x1C)
-#define STM32_GPIO_AFRL_OFF(b)      REG32((b) + 0x20)
-#define STM32_GPIO_AFRH_OFF(b)      REG32((b) + 0x24)
+#define STM32_GPIO_MODER(b)     REG32((b) + 0x00)
+#define STM32_GPIO_OTYPER(b)    REG16((b) + 0x04)
+#define STM32_GPIO_OSPEEDR(b)   REG32((b) + 0x08)
+#define STM32_GPIO_PUPDR(b)     REG32((b) + 0x0C)
+#define STM32_GPIO_IDR(b)       REG16((b) + 0x10)
+#define STM32_GPIO_ODR(b)       REG16((b) + 0x14)
+#define STM32_GPIO_BSRR(b)      REG32((b) + 0x18)
+#define STM32_GPIO_LCKR(b)      REG32((b) + 0x1C)
+#define STM32_GPIO_AFRL(b)      REG32((b) + 0x20)
+#define STM32_GPIO_AFRH(b)      REG32((b) + 0x24)
 
 #define GPIO_ALT_SYS                 0x0
 #define GPIO_ALT_TIM2                0x1
@@ -215,13 +215,13 @@
 #define STM32_GPIOF_BASE            0x4001c000
 #define STM32_GPIOG_BASE            0x40012000
 
-#define STM32_GPIO_CRL_OFF(b)       REG32((b) + 0x00)
-#define STM32_GPIO_CRH_OFF(b)       REG32((b) + 0x04)
-#define STM32_GPIO_IDR_OFF(b)       REG16((b) + 0x08)
-#define STM32_GPIO_ODR_OFF(b)       REG16((b) + 0x0c)
-#define STM32_GPIO_BSRR_OFF(b)      REG32((b) + 0x10)
-#define STM32_GPIO_BRR_OFF(b)       REG32((b) + 0x14)
-#define STM32_GPIO_LCKR_OFF(b)      REG32((b) + 0x18)
+#define STM32_GPIO_CRL(b)       REG32((b) + 0x00)
+#define STM32_GPIO_CRH(b)       REG32((b) + 0x04)
+#define STM32_GPIO_IDR(b)       REG16((b) + 0x08)
+#define STM32_GPIO_ODR(b)       REG16((b) + 0x0c)
+#define STM32_GPIO_BSRR(b)      REG32((b) + 0x10)
+#define STM32_GPIO_BRR(b)       REG32((b) + 0x14)
+#define STM32_GPIO_LCKR(b)      REG32((b) + 0x18)
 
 #define STM32_AFIO_BASE             0x40010000
 #define STM32_AFIO_EXTICR(n)        REG32(STM32_AFIO_BASE + 8 + 4 * (n))