diff options
| author | Bill Richardson <wfrichar@chromium.org> | 2013-04-26 20:02:07 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-04-29 11:05:08 -0700 |
| commit | d9bddaa0722d2b95c9b72c9c3a24c33053381311 (patch) | |
| tree | 9db87c5dbf220fed30d9caca8a10a0aa2a61039c /chip | |
| parent | 7cebaa0a017d734ae9dda19a39fd867463f785c6 (diff) | |
| download | chrome-ec-d9bddaa0722d2b95c9b72c9c3a24c33053381311.tar.gz | |
Improved the BUILD_ASSERT macro to work outside of functions.
This will let us check the size of static array initializers.
Also moved this macro definition and ARRAY_SIZE into a new "tricks.h"
header, so that userspace utils can use it too.
BUG=none
BRANCH=none
TEST=manual
Built everything, tested on Link. Tried various assertions.
Change-Id: I612891108ea37dbca3572e0f25ab54a7bc0ed860
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49417
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/clock-stm32f100.c | 2 | ||||
| -rw-r--r-- | chip/stm32/clock-stm32l15x.c | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/chip/stm32/clock-stm32f100.c b/chip/stm32/clock-stm32f100.c index ae919ca1b1..0dd63f456b 100644 --- a/chip/stm32/clock-stm32f100.c +++ b/chip/stm32/clock-stm32f100.c @@ -141,6 +141,7 @@ DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1); #else #error "Need board-specific clock settings" #endif +BUILD_ASSERT(CPU_CLOCK == DESIRED_CPU_CLOCK); static void config_hispeed_clock(void) { @@ -153,7 +154,6 @@ static void config_hispeed_clock(void) ; } - BUILD_ASSERT(CPU_CLOCK == DESIRED_CPU_CLOCK); STM32_RCC_CFGR = RCC_CFGR; /* Enable the PLL */ STM32_RCC_CR |= 1 << 24; diff --git a/chip/stm32/clock-stm32l15x.c b/chip/stm32/clock-stm32l15x.c index 687919f73b..057888f68f 100644 --- a/chip/stm32/clock-stm32l15x.c +++ b/chip/stm32/clock-stm32l15x.c @@ -10,6 +10,8 @@ #include "registers.h" #include "util.h" +BUILD_ASSERT(CPU_CLOCK == 16000000); + void enable_sleep(uint32_t mask) { /* low power mode not implemented */ @@ -60,7 +62,6 @@ void clock_init(void) * stays on HSI, no prescaler, PLLSRC = HSI, PLLMUL = x3, PLLDIV = /3, * no MCO => PLLVCO = 48 MHz and PLLCLK = 16 Mhz */ - BUILD_ASSERT(CPU_CLOCK == 16000000); STM32_RCC_CFGR = 0x00800001; /* Enable the PLL */ STM32_RCC_CR |= 1 << 24; |