stm32: Clean up DMA register usage

Bitfields are now in registers.h where they belong.

BUG=chrome-os-partner:20529
BRANCH=none
TEST='crosec test' from u-boot still works

Change-Id: I726550a32b61111c906c1b10c628c5e47eff74fb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60179

5 files changed, 195 insertions, 130 deletions

diff --git a/chip/stm32/adc.c b/chip/stm32/adc.c
index d65ffed2c0..22032cfdb8 100644
--- a/chip/stm32/adc.c
+++ b/chip/stm32/adc.c
@@ -21,8 +21,8 @@ struct mutex adc_lock;
 static int watchdog_ain_id;
 
 static const struct dma_option dma_adc_option = {
-	DMAC_ADC, (void *)&STM32_ADC_DR,
-	DMA_MSIZE_HALF_WORD | DMA_PSIZE_HALF_WORD
+	STM32_DMAC_ADC, (void *)&STM32_ADC_DR,
+	STM32_DMA_CCR_MSIZE_16_BIT | STM32_DMA_CCR_PSIZE_16_BIT,
 };
 
 static inline void adc_set_channel(int sample_id, int channel)
@@ -235,7 +235,7 @@ int adc_read_all_channels(int *data)
 	/* Start conversion */
 	STM32_ADC_CR2 |= (1 << 0); /* ADON */
 
-	if (dma_wait(DMAC_ADC)) {
+	if (dma_wait(STM32_DMAC_ADC)) {
 		ret = EC_ERROR_UNKNOWN;
 		goto exit_all_channels;
 	}
diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c
index aae499e4b2..c4eb08d4ec 100644
--- a/chip/stm32/dma.c
+++ b/chip/stm32/dma.c
@@ -17,17 +17,7 @@
 #define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args)
 
 /* Task IDs for the interrupt handlers to wake up */
-static task_id_t id[DMA_NUM_CHANNELS];
-
-/* Registers for the DMA controller */
-struct dma_ctlr {
-	uint32_t	isr;
-	uint32_t	ifcr;
-	dma_channel_t chan[DMA_NUM_CHANNELS];
-};
-
-/* Always use dma_ctlr_t so volatile keyword is included! */
-typedef volatile struct dma_ctlr dma_ctlr_t;
+static task_id_t id[STM32_DMAC_COUNT];
 
 /**
  * Return the IRQ for the DMA channel
@@ -40,101 +30,86 @@ static int dma_get_irq(enum dma_channel channel)
 	return STM32_IRQ_DMA_CHANNEL_1 + channel;
 }
 
-/**
- * Get a pointer to the DMA peripheral controller that owns the channel
- *
- * @param channel	Channel number to get the controller for (DMAC_...)
- * @return pointer to DMA channel registers
- */
-static dma_ctlr_t *dma_get_ctlr(void)
-{
-	return (dma_ctlr_t *)STM32_DMA1_BASE;
-}
-
 /*
  * Note, you must decrement the channel value by 1 from what is specified
  * in the datasheets, as they index from 1 and this indexes from 0!
  */
-dma_channel_t *dma_get_channel(enum dma_channel channel)
+stm32_dma_chan_t *dma_get_channel(enum dma_channel channel)
 {
-	dma_ctlr_t *dma = dma_get_ctlr();
-
-	/* Get a pointer to the correct controller and channel */
-	ASSERT(channel < DMA_NUM_CHANNELS);
+	stm32_dma_regs_t *dma = STM32_DMA1_REGS;
 
 	return &dma->chan[channel];
 }
 
 void dma_disable(enum dma_channel channel)
 {
-	dma_channel_t *chan = dma_get_channel(channel);
+	stm32_dma_chan_t *chan = dma_get_channel(channel);
 
-	if (chan->ccr & DMA_EN)
-		chan->ccr &= ~DMA_EN;
+	if (chan->ccr & STM32_DMA_CCR_EN)
+		chan->ccr &= ~STM32_DMA_CCR_EN;
 }
 
 /**
  * Prepare a channel for use and start it
  *
- * @param chan		Channel number to read (DMAC_...)
+ * @param chan		Channel to read
  * @param count		Number of bytes to transfer
  * @param periph	Pointer to peripheral data register
  * @param memory	Pointer to memory address for receive/transmit
  * @param flags		DMA flags for the control register, normally:
-				DMA_MINC_MASK |
- *				(DMA_DIR_FROM_MEM_MASK for tx
- *				0 for rx)
+ *				STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR for tx
+ *				0 for rx
  */
-static void prepare_channel(dma_channel_t *chan, unsigned count,
+static void prepare_channel(stm32_dma_chan_t *chan, unsigned count,
 		void *periph, void *memory, unsigned flags)
 {
-	uint32_t ctrl = DMA_PL_VERY_HIGH << DMA_PL_SHIFT;
+	uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH;
 
-	if (chan->ccr & DMA_EN)
-		chan->ccr &= ~DMA_EN;
+	if (chan->ccr & STM32_DMA_CCR_EN)
+		chan->ccr &= ~STM32_DMA_CCR_EN;
 
 	/* Following the order in Doc ID 15965 Rev 5 p194 */
 	chan->cpar = (uint32_t)periph;
 	chan->cmar = (uint32_t)memory;
 	chan->cndtr = count;
-	chan->ccr = ctrl;
-
-	ctrl |= flags;
-	chan->ccr = ctrl;
+	chan->ccr = ccr;
+	ccr |= flags;
+	chan->ccr = ccr;
 }
 
-void dma_go(dma_channel_t *chan)
+void dma_go(stm32_dma_chan_t *chan)
 {
 	/* Fire it up */
-	chan->ccr |= DMA_EN;
+	chan->ccr |= STM32_DMA_CCR_EN;
 }
 
 void dma_prepare_tx(const struct dma_option *option, unsigned count,
 		    const void *memory)
 {
-	dma_channel_t *chan = dma_get_channel(option->channel);
+	stm32_dma_chan_t *chan = dma_get_channel(option->channel);
 
 	/*
 	 * Cast away const for memory pointer; this is ok because we know
 	 * we're preparing the channel for transmit.
 	 */
 	prepare_channel(chan, count, option->periph, (void *)memory,
-			DMA_MINC_MASK | DMA_DIR_FROM_MEM_MASK | option->flags);
+			STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR |
+			option->flags);
 }
 
 void dma_start_rx(const struct dma_option *option, unsigned count,
 		  void *memory)
 {
-	dma_channel_t *chan = dma_get_channel(option->channel);
+	stm32_dma_chan_t *chan = dma_get_channel(option->channel);
 
 	prepare_channel(chan, count, option->periph, memory,
-			DMA_MINC_MASK | option->flags);
+			STM32_DMA_CCR_MINC | option->flags);
 	dma_go(chan);
 }
 
-int dma_bytes_done(dma_channel_t *chan, int orig_count)
+int dma_bytes_done(stm32_dma_chan_t *chan, int orig_count)
 {
-	if (!(chan->ccr & DMA_EN))
+	if (!(chan->ccr & STM32_DMA_CCR_EN))
 		return 0;
 	return orig_count - chan->cndtr;
 }
@@ -142,8 +117,8 @@ int dma_bytes_done(dma_channel_t *chan, int orig_count)
 #ifdef CONFIG_DMA_HELP
 void dma_dump(enum dma_channel channel)
 {
-	dma_ctlr_t *dma = dma_get_ctlr();
-	dma_channel_t *chan = dma_get_channel(channel);
+	stm32_dma_regs_t *dma = STM32_DMA1_REGS;
+	stm32_dma_chan_t *chan = dma_get_channel(channel);
 
 	CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr,
 		chan->cndtr, chan->cpar, chan->cmar);
@@ -155,7 +130,7 @@ void dma_dump(enum dma_channel channel)
 
 void dma_check(enum dma_channel channel, char *buf)
 {
-	dma_channel_t *chan;
+	stm32_dma_chan_t *chan;
 	int count;
 	int i;
 
@@ -175,8 +150,8 @@ void dma_check(enum dma_channel channel, char *buf)
 /* Run a check of memory-to-memory DMA */
 void dma_test(void)
 {
-	dma_channel_t *chan = dma_get_channel(channel);
-	unsigned channel = 3;
+	enum dma_channel channel = STM32_DMAC_CH4;
+	stm32_dma_chan_t *chan = dma_get_channel(channel);
 	uint32_t ctrl;
 	char periph[16], memory[16];
 	unsigned count = sizeof(periph);
@@ -190,18 +165,17 @@ void dma_test(void)
 	chan->cpar = (uint32_t)periph;
 	chan->cmar = (uint32_t)memory;
 	chan->cndtr = count;
-	ctrl = DMA_PL_MEDIUM << DMA_PL_SHIFT;
+	ctrl = STM32_DMA_CCR_PL_MEDIUM;
 	chan->ccr = ctrl;
 
-	ctrl |= DMA_MINC_MASK; /* | DMA_DIR_FROM_MEM_MASK */;
-	ctrl |= 1 << 14; /* MEM2MEM */
-	ctrl |= 1 << 6;  /* PINC */
-/*	ctrl |= 2 << 10; */
-/*	ctrl |= 2 << 8; */
+	ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */;
+	ctrl |= STM32_DMA_CCR_MEM2MEM;
+	ctrl |= STM32_DMA_CCR_PINC;
+/*	ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */
+/*	ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */
 	chan->ccr = ctrl;
+	chan->ccr = ctrl | STM32_DMA_CCR_EN;
 
-	ctrl |= DMA_EN;
-	chan->ccr = ctrl;
 	for (i = 0; i < count; i++)
 		CPRINTF("%d/%d ", periph[i], memory[i]);
 	CPRINTF("\ncount=%d\n", chan->cndtr);
@@ -213,86 +187,86 @@ static void dma_init(void)
 	int i;
 
 	/* Enable DMA1; current chips don't have DMA2 */
-	STM32_RCC_AHBENR |= RCC_AHBENR_DMA1EN;
+	STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1;
 
 	/* Initialize data for interrupt handlers */
-	for (i = 0; i < DMA_NUM_CHANNELS; i++)
+	for (i = 0; i < STM32_DMAC_COUNT; i++)
 		id[i] = TASK_ID_INVALID;
 }
 DECLARE_HOOK(HOOK_INIT, dma_init, HOOK_PRIO_INIT_DMA);
 
 int dma_wait(enum dma_channel channel)
 {
-	dma_ctlr_t *dma = dma_get_ctlr();
-	uint32_t mask = DMA_TCIF(channel);
+	stm32_dma_regs_t *dma = STM32_DMA1_REGS;
+	const uint32_t mask = STM32_DMA_ISR_TCIF(channel);
 	timestamp_t deadline;
 
 	deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US;
 	while ((dma->isr & mask) != mask) {
 		if (deadline.val <= get_time().val)
 			return EC_ERROR_TIMEOUT;
-		else
-			udelay(DMA_POLLING_INTERVAL_US);
+
+		udelay(DMA_POLLING_INTERVAL_US);
 	}
 	return EC_SUCCESS;
 }
 
 void dma_enable_tc_interrupt(enum dma_channel channel)
 {
-	dma_channel_t *chan = dma_get_channel(channel);
+	stm32_dma_chan_t *chan = dma_get_channel(channel);
 
 	/* Store task ID so the ISR knows which task to wake */
 	id[channel] = task_get_current();
 
-	chan->ccr |= DMA_TCIE;
+	chan->ccr |= STM32_DMA_CCR_TCIE;
 	task_enable_irq(dma_get_irq(channel));
 }
 
 void dma_disable_tc_interrupt(enum dma_channel channel)
 {
-	dma_channel_t *chan = dma_get_channel(channel);
+	stm32_dma_chan_t *chan = dma_get_channel(channel);
 
 	id[channel] = TASK_ID_INVALID;
 
-	chan->ccr &= ~DMA_TCIE;
+	chan->ccr &= ~STM32_DMA_CCR_TCIE;
 	task_disable_irq(dma_get_irq(channel));
 }
 
 void dma_clear_isr(enum dma_channel channel)
 {
-	dma_ctlr_t *dma = dma_get_ctlr();
+	stm32_dma_regs_t *dma = STM32_DMA1_REGS;
 
-	dma->ifcr |= 0x0f << (4 * channel);
+	dma->ifcr |= STM32_DMA_ISR_ALL(channel);
 }
 
 static void dma_event_interrupt_channel_4(void)
 {
-	dma_clear_isr(DMAC_CH4);
-	if (id[DMAC_CH4] != TASK_ID_INVALID)
-		task_wake(id[DMAC_CH4]);
+	dma_clear_isr(STM32_DMAC_CH4);
+	if (id[STM32_DMAC_CH4] != TASK_ID_INVALID)
+		task_wake(id[STM32_DMAC_CH4]);
 }
 DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4, dma_event_interrupt_channel_4, 3);
 
 static void dma_event_interrupt_channel_5(void)
 {
-	dma_clear_isr(DMAC_CH5);
-	if (id[DMAC_CH5] != TASK_ID_INVALID)
-		task_wake(id[DMAC_CH5]);
+	dma_clear_isr(STM32_DMAC_CH5);
+	if (id[STM32_DMAC_CH5] != TASK_ID_INVALID)
+		task_wake(id[STM32_DMAC_CH5]);
 }
 DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_5, dma_event_interrupt_channel_5, 3);
 
 static void dma_event_interrupt_channel_6(void)
 {
-	dma_clear_isr(DMAC_CH6);
-	if (id[DMAC_CH6] != TASK_ID_INVALID)
-		task_wake(id[DMAC_CH6]);
+	dma_clear_isr(STM32_DMAC_CH6);
+	if (id[STM32_DMAC_CH6] != TASK_ID_INVALID)
+		task_wake(id[STM32_DMAC_CH6]);
 }
 DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_6, dma_event_interrupt_channel_6, 3);
 
 static void dma_event_interrupt_channel_7(void)
 {
-	dma_clear_isr(DMAC_CH7);
-	if (id[DMAC_CH7] != TASK_ID_INVALID)
-		task_wake(id[DMAC_CH7]);
+	dma_clear_isr(STM32_DMAC_CH7);
+	if (id[STM32_DMAC_CH7] != TASK_ID_INVALID)
+		task_wake(id[STM32_DMAC_CH7]);
 }
 DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_7, dma_event_interrupt_channel_7, 3);
diff --git a/chip/stm32/i2c-stm32f100.c b/chip/stm32/i2c-stm32f100.c
index a76987ac74..3cdcbe84fd 100644
--- a/chip/stm32/i2c-stm32f100.c
+++ b/chip/stm32/i2c-stm32f100.c
@@ -61,10 +61,14 @@
 #define I2C2      STM32_I2C2_PORT
 
 /* Select the DMA channels matching the board configuration */
-#define DMAC_SLAVE_TX ((I2C_PORT_SLAVE) ? DMAC_I2C2_TX : DMAC_I2C1_TX)
-#define DMAC_SLAVE_RX ((I2C_PORT_SLAVE) ? DMAC_I2C2_RX : DMAC_I2C1_RX)
-#define DMAC_HOST_TX  ((I2C_PORT_HOST) ? DMAC_I2C2_TX : DMAC_I2C1_TX)
-#define DMAC_HOST_RX  ((I2C_PORT_HOST) ? DMAC_I2C2_RX : DMAC_I2C1_RX)
+#define DMAC_SLAVE_TX \
+	((I2C_PORT_SLAVE) ? STM32_DMAC_I2C2_TX : STM32_DMAC_I2C1_TX)
+#define DMAC_SLAVE_RX \
+	((I2C_PORT_SLAVE) ? STM32_DMAC_I2C2_RX : STM32_DMAC_I2C1_RX)
+#define DMAC_HOST_TX \
+	((I2C_PORT_HOST) ? STM32_DMAC_I2C2_TX : STM32_DMAC_I2C1_TX)
+#define DMAC_HOST_RX \
+	((I2C_PORT_HOST) ? STM32_DMAC_I2C2_RX : STM32_DMAC_I2C1_RX)
 
 enum {
 	/*
@@ -80,17 +84,17 @@ enum {
 };
 
 static const struct dma_option dma_tx_option[I2C_PORT_COUNT] = {
-	{DMAC_I2C1_TX, (void *)&STM32_I2C_DR(I2C1),
-	 DMA_MSIZE_BYTE | DMA_PSIZE_HALF_WORD},
-	{DMAC_I2C2_TX, (void *)&STM32_I2C_DR(I2C2),
-	 DMA_MSIZE_BYTE | DMA_PSIZE_HALF_WORD},
+	{STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(I2C1),
+	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT},
+	{STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(I2C2),
+	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT},
 };
 
 static const struct dma_option dma_rx_option[I2C_PORT_COUNT] = {
-	{DMAC_I2C1_RX, (void *)&STM32_I2C_DR(I2C1),
-	 DMA_MSIZE_BYTE | DMA_PSIZE_HALF_WORD},
-	{DMAC_I2C2_RX, (void *)&STM32_I2C_DR(I2C2),
-	 DMA_MSIZE_BYTE | DMA_PSIZE_HALF_WORD},
+	{STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(I2C1),
+	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT},
+	{STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(I2C2),
+	 STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT},
 };
 
 static uint16_t i2c_sr1[I2C_PORT_COUNT];
@@ -127,7 +131,7 @@ static void i2c_init_port(unsigned int port);
 
 static int i2c_write_raw_slave(int port, void *buf, int len)
 {
-	dma_channel_t *chan;
+	stm32_dma_chan_t *chan;
 	int rv;
 
 	/* we don't want to race with TxE interrupt event */
@@ -716,7 +720,7 @@ static int i2c_master_transmit(int port, int slave_addr, const uint8_t *data,
 
 	disable_ack(port);
 
-	/* Configuring DMA1 channel DMAC_I2X_TX */
+	/* Configure DMA channel for TX to host */
 	dma_prepare_tx(dma_tx_option + port, size, data);
 	dma_enable_tc_interrupt(DMAC_HOST_TX);
 
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 673ff1e83d..f4f054b99e 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -346,7 +346,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32_RCC_APB1LPENR         REG32(STM32_RCC_BASE + 0x30)
 #define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x34)
 
-#define RCC_AHBENR_DMA1EN           (1 << 24)
+#define STM32_RCC_HB_DMA1		(1 << 24)
 
 #define STM32_SYSCFG_BASE           0x40010000
 
@@ -369,7 +369,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #define STM32_RCC_CSR               REG32(STM32_RCC_BASE + 0x24)
 #define STM32_RCC_CFGR2             REG32(STM32_RCC_BASE + 0x2c) /* STM32F100 */
 
-#define RCC_AHBENR_DMA1EN           (1 << 0)
+#define STM32_RCC_HB_DMA1		(1 << 0)
 
 #else
 #error Unsupported chip variant
@@ -599,26 +599,113 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_ADC_DR               REG32(STM32_ADC1_BASE + 0x4C)
 #endif
 
-/* --- MISC --- */
+/* --- DMA --- */
 
-#define STM32_RI_BASE               0x40007C04
-#define STM32_COMP_BASE             0x40007C00
-#define STM32_CEC_BASE              0x40007800 /* STM32F100 only */
-#define STM32_DAC_BASE              0x40007400
-#define STM32_CRC_BASE              0x40023000
-#define STM32_LCD_BASE              0x40002400
 #if defined(CHIP_VARIANT_stm32l15x)
 #define STM32_DMA1_BASE             0x40026000
-#define STM32_DMA2_BASE             0x40026400
 #elif defined(CHIP_VARIANT_stm32f100) || defined(CHIP_VARIANT_stm32f10x)
 #define STM32_DMA1_BASE             0x40020000
-/* FIXME: DMA2 is only available on high-density devices, but is used as part
- * of a sanity check in dma.c */
-#define STM32_DMA2_BASE             0x40020400
 #else
 #error Unsupported chip variant
 #endif
 
+/*
+ * Available DMA channels, numbered from 0.
+ *
+ * Note: The STM datasheet tends to number things from 1. We should ask
+ * the European elevator engineers to talk to MCU engineer counterparts
+ * about this.  This means that if the datasheet refers to channel n,
+ * you need to use STM32_DMAC_CHn (=n-1) in the code.
+ *
+ * Also note that channels are overloaded; obviously you can only use one
+ * function on each channel at a time.
+ */
+enum dma_channel {
+	/* Channel numbers */
+	STM32_DMAC_CH1 = 0,
+	STM32_DMAC_CH2 = 1,
+	STM32_DMAC_CH3 = 2,
+	STM32_DMAC_CH4 = 3,
+	STM32_DMAC_CH5 = 4,
+	STM32_DMAC_CH6 = 5,
+	STM32_DMAC_CH7 = 6,
+
+	/* Channel functions */
+	STM32_DMAC_ADC = STM32_DMAC_CH1,
+	STM32_DMAC_SPI1_RX = STM32_DMAC_CH2,
+	STM32_DMAC_SPI1_TX = STM32_DMAC_CH3,
+	STM32_DMAC_I2C2_TX = STM32_DMAC_CH4,
+	STM32_DMAC_I2C2_RX = STM32_DMAC_CH5,
+	STM32_DMAC_USART1_TX = STM32_DMAC_CH4,
+	STM32_DMAC_USART1_RX = STM32_DMAC_CH5,
+	STM32_DMAC_I2C1_TX = STM32_DMAC_CH6,
+	STM32_DMAC_I2C1_RX = STM32_DMAC_CH7,
+
+	/* Only DMA1 (with 7 channels) is present on STM32F100 and STM32L151x */
+	STM32_DMAC_COUNT = 7,
+};
+
+/* Registers for a single channel of the DMA controller */
+struct stm32_dma_chan {
+	uint32_t	ccr;		/* Control */
+	uint32_t	cndtr;		/* Number of data to transfer */
+	uint32_t	cpar;		/* Peripheral address */
+	uint32_t	cmar;		/* Memory address */
+	uint32_t	reserved;
+};
+
+/* Always use stm32_dma_chan_t so volatile keyword is included! */
+typedef volatile struct stm32_dma_chan stm32_dma_chan_t;
+
+/* Registers for the DMA controller */
+struct stm32_dma_regs {
+	uint32_t	isr;
+	uint32_t	ifcr;
+	stm32_dma_chan_t chan[STM32_DMAC_COUNT];
+};
+
+/* Always use stm32_dma_regs_t so volatile keyword is included! */
+typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
+
+#define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE)
+
+/* Bits for DMA controller regs (isr and ifcr) */
+#define STM32_DMA_ISR_MASK(channel, mask) ((mask) << (4 * (channel)))
+#define STM32_DMA_ISR_GIF(channel)	STM32_DMA_ISR_MASK(channel, 1 << 0)
+#define STM32_DMA_ISR_TCIF(channel)	STM32_DMA_ISR_MASK(channel, 1 << 1)
+#define STM32_DMA_ISR_HTIF(channel)	STM32_DMA_ISR_MASK(channel, 1 << 2)
+#define STM32_DMA_ISR_TEIF(channel)	STM32_DMA_ISR_MASK(channel, 1 << 3)
+#define STM32_DMA_ISR_ALL(channel)	STM32_DMA_ISR_MASK(channel, 0x0f)
+
+/* Bits for DMA channel regs */
+#define STM32_DMA_CCR_EN		(1 << 0)
+#define STM32_DMA_CCR_TCIE		(1 << 1)
+#define STM32_DMA_CCR_HTIE		(1 << 2)
+#define STM32_DMA_CCR_TEIE		(1 << 3)
+#define STM32_DMA_CCR_DIR		(1 << 4)
+#define STM32_DMA_CCR_CIRC		(1 << 5)
+#define STM32_DMA_CCR_PINC		(1 << 6)
+#define STM32_DMA_CCR_MINC		(1 << 7)
+#define STM32_DMA_CCR_PSIZE_8_BIT	(0 << 8)
+#define STM32_DMA_CCR_PSIZE_16_BIT	(1 << 8)
+#define STM32_DMA_CCR_PSIZE_32_BIT	(2 << 8)
+#define STM32_DMA_CCR_MSIZE_8_BIT	(0 << 10)
+#define STM32_DMA_CCR_MSIZE_16_BIT	(1 << 10)
+#define STM32_DMA_CCR_MSIZE_32_BIT	(2 << 10)
+#define STM32_DMA_CCR_PL_LOW		(0 << 12)
+#define STM32_DMA_CCR_PL_MEDIUM		(1 << 12)
+#define STM32_DMA_CCR_PL_HIGH		(2 << 12)
+#define STM32_DMA_CCR_PL_VERY_HIGH	(3 << 12)
+#define STM32_DMA_CCR_MEM2MEM		(1 << 14)
+
+/* --- MISC --- */
+
+#define STM32_RI_BASE               0x40007C04
+#define STM32_COMP_BASE             0x40007C00
+#define STM32_CEC_BASE              0x40007800 /* STM32F100 only */
+#define STM32_DAC_BASE              0x40007400
+#define STM32_CRC_BASE              0x40023000
+#define STM32_LCD_BASE              0x40002400
 #define STM32_FSMC_BASE             0xA0000000 /* STM32F10x only */
 #define STM32_USB_OTG_FS_BASE       0x50000000 /* STM32F10x only */
 #define STM32_ETHERNET_BASE         0x40028000 /* STM32F10x only */
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
index 69333c34b7..c2a6044da8 100644
--- a/chip/stm32/spi.c
+++ b/chip/stm32/spi.c
@@ -24,13 +24,13 @@
 
 /* DMA channel option */
 static const struct dma_option dma_tx_option = {
-	DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr,
-	DMA_MSIZE_BYTE | DMA_PSIZE_HALF_WORD
+	STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr,
+	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT
 };
 
 static const struct dma_option dma_rx_option = {
-	DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr,
-	DMA_MSIZE_BYTE | DMA_PSIZE_HALF_WORD
+	STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr,
+	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT
 };
 
 /*
@@ -108,7 +108,7 @@ static const uint8_t out_preamble[4] = {
  * @param nss_mask	Bit to check in GPIO register (when high, we abort)
  * @return 0 if bytes received, -1 if we hit a timeout or NSS went high
  */
-static int wait_for_bytes(dma_channel_t *rxdma, int needed,
+static int wait_for_bytes(stm32_dma_chan_t *rxdma, int needed,
 			  uint16_t *nss_reg, uint32_t nss_mask)
 {
 	timestamp_t deadline;
@@ -165,7 +165,7 @@ static int wait_for_bytes(dma_channel_t *rxdma, int needed,
  *			SPI_MSG_HEADER_LEN bytes into out_msg
  * @param msg_len	Number of message bytes to send
  */
-static void reply(dma_channel_t *txdma,
+static void reply(stm32_dma_chan_t *txdma,
 		  enum ec_status status, char *msg_ptr, int msg_len)
 {
 	char *msg;
@@ -219,7 +219,7 @@ static void setup_for_transaction(void)
 
 	/* write 0xfd which will be our default output value */
 	spi->dr = 0xfd;
-	dma_disable(DMAC_SPI1_TX);
+	dma_disable(STM32_DMAC_SPI1_TX);
 	*in_msg = 0xff;
 
 	/* read a byte in case there is one, and the rx dma gets it */
@@ -237,7 +237,7 @@ static void setup_for_transaction(void)
 static void spi_send_response(struct host_cmd_handler_args *args)
 {
 	enum ec_status result = args->result;
-	dma_channel_t *txdma;
+	stm32_dma_chan_t *txdma;
 
 	/* If we are too late, don't bother */
 	if (!active)
@@ -251,7 +251,7 @@ static void spi_send_response(struct host_cmd_handler_args *args)
 		ASSERT(args->response == out_msg + SPI_MSG_HEADER_LEN);
 
 	/* Transmit the reply */
-	txdma = dma_get_channel(DMAC_SPI1_TX);
+	txdma = dma_get_channel(STM32_DMAC_SPI1_TX);
 	reply(txdma, result, args->response, args->response_size);
 }
 
@@ -264,14 +264,14 @@ static void spi_send_response(struct host_cmd_handler_args *args)
  */
 static void spi_send_response_packet(struct host_packet *pkt)
 {
-	dma_channel_t *txdma;
+	stm32_dma_chan_t *txdma;
 
 	/* If we are too late, don't bother */
 	if (!active)
 		return;
 
 	/* Transmit the reply */
-	txdma = dma_get_channel(DMAC_SPI1_TX);
+	txdma = dma_get_channel(STM32_DMAC_SPI1_TX);
 	dma_prepare_tx(&dma_tx_option,
 		       sizeof(out_preamble) + pkt->response_size, out_msg);
 	dma_go(txdma);
@@ -287,7 +287,7 @@ static void spi_send_response_packet(struct host_packet *pkt)
  */
 void spi_event(enum gpio_signal signal)
 {
-	dma_channel_t *rxdma;
+	stm32_dma_chan_t *rxdma;
 	uint16_t *nss_reg;
 	uint32_t nss_mask;
 
@@ -307,7 +307,7 @@ void spi_event(enum gpio_signal signal)
 
 	/* Otherwise, NSS is low and we're now inside a transaction */
 	active = 1;
-	rxdma = dma_get_channel(DMAC_SPI1_RX);
+	rxdma = dma_get_channel(STM32_DMAC_SPI1_RX);
 
 	/* Wait for version, command, length bytes */
 	if (wait_for_bytes(rxdma, 3, nss_reg, nss_mask)) {