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author | Randall Spangler <rspangler@chromium.org> | 2013-07-24 11:19:10 -0700 |
---|---|---|
committer | ChromeBot <chrome-bot@google.com> | 2013-07-24 14:05:17 -0700 |
commit | fe660aa3729aa6f468a62f4e6c37f3dd5c85503d (patch) | |
tree | 3d784cdf240e80fd31c2fdc291c24ddaca6b7d08 /chip | |
parent | 596480de062da815326071630ebf2348ce1c02ac (diff) | |
download | chrome-ec-fe660aa3729aa6f468a62f4e6c37f3dd5c85503d.tar.gz |
Standardize concatenation macros
To create a token by concatenating already-defined macros and new
text, it's necessary to use multiple levels of macro. We'd already
done that in several places in the code such as STM32_CAT; this now
standardizes it into a single place.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=Build all platforms; examine ec.RO.map to see that irq_*_handler and prio_* symbols
evaluated the same as before. (Other macro evaluations would simply fail to compile
if they were incorrect, since the concatenated tokens wouldn't fully expand.)
Change-Id: Ic9bf11d27881a84507fe7b6096dab6217c6c6dc7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63231
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/lm4/watchdog.c | 2 | ||||
-rw-r--r-- | chip/stm32/hwtimer.c | 10 | ||||
-rw-r--r-- | chip/stm32/registers.h | 12 |
3 files changed, 10 insertions, 14 deletions
diff --git a/chip/lm4/watchdog.c b/chip/lm4/watchdog.c index 7bc7aa8a60..ef817cf715 100644 --- a/chip/lm4/watchdog.c +++ b/chip/lm4/watchdog.c @@ -48,7 +48,7 @@ void IRQ_HANDLER(LM4_IRQ_WATCHDOG)(void) "b task_resched_if_needed\n" : : [irq] "i" (LM4_IRQ_WATCHDOG)); } -const struct irq_priority IRQ_BUILD_NAME(prio_, LM4_IRQ_WATCHDOG, ) +const struct irq_priority IRQ_PRIORITY(LM4_IRQ_WATCHDOG) __attribute__((section(".rodata.irqprio"))) = {LM4_IRQ_WATCHDOG, 0}; /* put the watchdog at the highest priority */ diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index 6ac971f44d..abd2d2ba7b 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -51,14 +51,14 @@ #define STM32_TIM_TS_SLAVE_9_MASTER_3 1 #define STM32_TIM_TS_SLAVE_9_MASTER_10 2 #define STM32_TIM_TS_SLAVE_9_MASTER_11 3 -#define TSMAP1(slave, master) STM32_TIM_TS_SLAVE_ ## slave ## _MASTER_ ## master -#define TSMAP(slave, master) TSMAP1(slave, master) +#define TSMAP(slave, master) \ + CONCAT4(STM32_TIM_TS_SLAVE_, slave, _MASTER_, master) /* * Timers are defined per board. This gives us flexibility to work around * timers which are dedicated to board-specific PWM sources. */ -#define IRQ_TIM(n) STM32_CAT(STM32_IRQ_TIM, n, ) +#define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n) #define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB) #define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB) #define IRQ_WD IRQ_TIM(TIM_WATCHDOG) @@ -66,7 +66,7 @@ /* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */ #define STM32_IRQ_TIM1 STM32_IRQ_TIM1_UP_TIM16 -#define TIM_BASE(n) STM32_CAT(STM32_TIM, n, _BASE) +#define TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE) #define TIM_WD_BASE TIM_BASE(TIM_WATCHDOG) static uint32_t last_deadline; @@ -295,7 +295,7 @@ void IRQ_HANDLER(IRQ_WD)(void) "pop {r0, lr}\n" "b task_resched_if_needed\n"); } -const struct irq_priority IRQ_BUILD_NAME(prio_, IRQ_WD, ) +const struct irq_priority IRQ_PRIORITY(IRQ_WD) __attribute__((section(".rodata.irqprio"))) = {IRQ_WD, 0}; /* put the watchdog at the highest priority */ diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 48ebf1242b..0d7d14e9a2 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -10,9 +10,6 @@ #include "common.h" -/* concatenation helper */ -#define STM32_CAT(prefix, n, suffix) prefix ## n ## suffix - /* IRQ numbers */ #define STM32_IRQ_WWDG 0 #define STM32_IRQ_PVD 1 @@ -100,10 +97,9 @@ #define STM32_UART4_BASE 0x40004c00 /* STM32F100 and STM32F10x */ #define STM32_UART5_BASE 0x40005000 /* STM32F100 and STM32F10x */ -#define STM32_USART_BASE(n) STM32_CAT(STM32_USART, n, _BASE) +#define STM32_USART_BASE(n) CONCAT3(STM32_USART, n, _BASE) -#define STM32_USART_REG(n, offset) \ - REG16(STM32_CAT(STM32_USART, n, _BASE) + (offset)) +#define STM32_USART_REG(n, offset) REG16(STM32_USART_BASE(n) + (offset)) #define STM32_USART_SR(n) STM32_USART_REG(n, 0x00) #define STM32_USART_SR_RXNE (1 << 5) @@ -122,7 +118,7 @@ #define STM32_USART_CR3_ONEBIT (1 << 11) /* STM32L only */ #define STM32_USART_GTPR(n) STM32_USART_REG(n, 0x18) -#define STM32_IRQ_USART(n) STM32_CAT(STM32_IRQ_USART, n, ) +#define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n) /* --- TIMERS --- */ #define STM32_TIM1_BASE 0x40012c00 /* STM32F100 and STM32F10x */ @@ -150,7 +146,7 @@ #define STM32_TIM17_BASE 0x40014800 /* STM32F100 only */ #define STM32_TIM_REG(n, offset) \ - REG16(STM32_CAT(STM32_TIM, n, _BASE) + (offset)) + REG16(CONCAT3(STM32_TIM, n, _BASE) + (offset)) #define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) #define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) |