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authorVic (Chun-Ju) Yang <victoryang@chromium.org>2014-01-09 11:53:17 +0800
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-01-09 20:25:18 +0000
commitb6f8f36aa426b84d673464a15b37df669ecad57c (patch)
treeb11057afeb7954f476e0f2a9aadd00c1516f253b /chip
parent72481572aad731b3c2db20c41efb6d5a51812eaa (diff)
downloadchrome-ec-b6f8f36aa426b84d673464a15b37df669ecad57c.tar.gz
mec1322: Use internal SCI pin control
Instead of requiring a GPIO definition, default to using the internal SCI pin control. BUG=chrome-os-partner:24550 TEST=Trigger SCI and verify with logic analyzer BRANCH=None Change-Id: I13ac3b8f1031d3c56ea0b8f6a6ed0c1aa4e77bb1 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182010 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r--chip/mec1322/lpc.c13
-rw-r--r--chip/mec1322/registers.h12
2 files changed, 22 insertions, 3 deletions
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c
index fb3ace7438..3dc39a18e6 100644
--- a/chip/mec1322/lpc.c
+++ b/chip/mec1322/lpc.c
@@ -48,10 +48,15 @@ static void lpc_generate_smi(void)
static void lpc_generate_sci(void)
{
- /* TODO (crosbug.com/p/24550): Use EC_SCI# instead of GPIO */
- gpio_set_level(GPIO_PCH_SCI_L, 0);
+#ifdef CONFIG_SCI_GPIO
+ gpio_set_level(CONFIG_SCI_GPIO, 0);
udelay(65);
- gpio_set_level(GPIO_PCH_SCI_L, 1);
+ gpio_set_level(CONFIG_SCI_GPIO, 1);
+#else
+ MEC1322_ACPI_PM_STS |= 1;
+ udelay(65);
+ MEC1322_ACPI_PM_STS &= ~1;
+#endif
}
/**
@@ -158,6 +163,8 @@ static void setup_lpc(void)
if (ptr < 0x120000)
ptr = ptr - 0x118000 + 0x20000000;
+ gpio_config_module(MODULE_LPC, 1);
+
/* Set up ACPI0 for 0x62/0x66 */
MEC1322_LPC_ACPI_EC0_BAR = 0x00628034;
MEC1322_INT_ENABLE(15) |= 1 << 6;
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h
index 5a5aa98f2b..47a839ed96 100644
--- a/chip/mec1322/registers.h
+++ b/chip/mec1322/registers.h
@@ -190,6 +190,18 @@ static inline uintptr_t gpio_port_base(int port_id)
#define MEC1322_ACPI_EC_BYTE_CTL(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x105)
#define MEC1322_ACPI_EC_OS2EC(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x108 + (y))
+#define MEC1322_ACPI_PM_RT_BASE 0x400f1400
+#define MEC1322_ACPI_PM1_STS1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x0)
+#define MEC1322_ACPI_PM1_STS2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x1)
+#define MEC1322_ACPI_PM1_EN1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x2)
+#define MEC1322_ACPI_PM1_EN2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x3)
+#define MEC1322_ACPI_PM1_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x4)
+#define MEC1322_ACPI_PM1_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x5)
+#define MEC1322_ACPI_PM2_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x6)
+#define MEC1322_ACPI_PM2_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x7)
+#define MEC1322_ACPI_PM_EC_BASE 0x400f1500
+#define MEC1322_ACPI_PM_STS REG8(MEC1322_ACPI_PM_EC_BASE + 0x10)
+
/* 8042 */
#define MEC1322_8042_BASE 0x400f0400