diff options
| author | Myles Watson <mylesgw@chromium.org> | 2015-02-19 15:58:31 -0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-03-02 21:37:13 +0000 |
| commit | 1f6f5d5333c34ddcb8337defa93f2c3ad3705c02 (patch) | |
| tree | db26b8277044d56a440341423651593ad54f7343 /chip | |
| parent | 65f049b977016273f93491f0d8b2c2d0a7549819 (diff) | |
| download | chrome-ec-1f6f5d5333c34ddcb8337defa93f2c3ad3705c02.tar.gz | |
nrf51: Reset clean up.
Use the values from the datasheet to report the reset reason.
TEST=hard reset, soft reset, wake from sleep with a GPIO
BRANCH=NONE
BUG=None
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Change-Id: I2a45741c9c17f0c2e4eb4b8b12d3231f407244dd
Reviewed-on: https://chromium-review.googlesource.com/254112
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Myles Watson <mylesgw@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/nrf51/gpio.c | 7 | ||||
| -rw-r--r-- | chip/nrf51/registers.h | 8 | ||||
| -rw-r--r-- | chip/nrf51/system.c | 19 |
3 files changed, 22 insertions, 12 deletions
diff --git a/chip/nrf51/gpio.c b/chip/nrf51/gpio.c index 40f5f03593..ccb453d0c2 100644 --- a/chip/nrf51/gpio.c +++ b/chip/nrf51/gpio.c @@ -126,7 +126,9 @@ void gpio_pre_init(void) int is_warm = 0; int i; - if (NRF51_POWER_RESETREAS & (1 << 2)) { + if (NRF51_POWER_RESETREAS & + (NRF51_POWER_RESETREAS_OFF | /* GPIO Wake */ + NRF51_POWER_RESETREAS_LPCOMP)) { /* This is a warm reboot */ is_warm = 1; } @@ -144,8 +146,7 @@ void gpio_pre_init(void) continue; /* - * If this is a warm reboot, don't set the output levels or - * we'll shut off the AP. + * If this is a warm reboot, don't set the output levels again. */ if (is_warm) flags &= ~(GPIO_LOW | GPIO_HIGH); diff --git a/chip/nrf51/registers.h b/chip/nrf51/registers.h index e60252a6d2..dab3a05fd1 100644 --- a/chip/nrf51/registers.h +++ b/chip/nrf51/registers.h @@ -147,6 +147,14 @@ #define NRF51_POWER_RESET REG32(NRF51_POWER_BASE + 0x544) #define NRF51_POWER_DCDCEN REG32(NRF51_POWER_BASE + 0x578) +#define NRF51_POWER_RESETREAS_RESETPIN 0x00001 +#define NRF51_POWER_RESETREAS_DOG 0x00002 +#define NRF51_POWER_RESETREAS_SREQ 0x00004 +#define NRF51_POWER_RESETREAS_LOCKUP 0x00008 +#define NRF51_POWER_RESETREAS_OFF 0x10000 +#define NRF51_POWER_RESETREAS_LPCOMP 0x20000 +#define NRF51_POWER_RESETREAS_DIF 0x40000 + /* * Clock diff --git a/chip/nrf51/system.c b/chip/nrf51/system.c index 687b889a69..86d78b3170 100644 --- a/chip/nrf51/system.c +++ b/chip/nrf51/system.c @@ -46,21 +46,22 @@ static void check_reset_cause(void) uint32_t flags = 0; uint32_t raw_cause = NRF51_POWER_RESETREAS; - if (raw_cause & 0x00000001) + if (raw_cause & NRF51_POWER_RESETREAS_RESETPIN) flags |= RESET_FLAG_RESET_PIN; - if (raw_cause & 0x00000002) + if (raw_cause & NRF51_POWER_RESETREAS_DOG) flags |= RESET_FLAG_WATCHDOG; - /* - * According to the data sheet, this bit is set by AIRCR.SYSRESETREQ. - * However, th reset from J-Link also sets this bit. This could mislead - * us. - */ - if (raw_cause & 0x00000004) + /* Note that the programmer uses a soft reset in debug mode. */ + if (raw_cause & NRF51_POWER_RESETREAS_SREQ) flags |= RESET_FLAG_SOFT; - if (raw_cause & 0x00070008) + if (raw_cause & (NRF51_POWER_RESETREAS_OFF | + NRF51_POWER_RESETREAS_LPCOMP)) + flags |= RESET_FLAG_WAKE_PIN; + + if (raw_cause & (NRF51_POWER_RESETREAS_LOCKUP | + NRF51_POWER_RESETREAS_DIF)) flags |= RESET_FLAG_OTHER; system_set_reset_flags(flags); |