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authorKevin K Wong <kevin.k.wong@intel.com>2015-04-01 22:34:59 -0700
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>2015-04-09 04:45:23 +0000
commit55c739b9a451871f742585ddda491105eef53662 (patch)
treead073d850109a9b9b785e8680225edafaf86b077 /chip
parente369986c6ed153f5cdae30a865765985934d32f4 (diff)
downloadchrome-ec-55c739b9a451871f742585ddda491105eef53662.tar.gz
mec1322: Added CONFIG_KEYBOARD_KSO_BASE to align KBD KSO00 pin to board design
MEC1322 KSO00~03 pin has an alternate JTAG function. For board that needs JTAG function, this #define allows hardware to use a different set of KSO pins. For example - Uses KSO04~16 instead of KSO00~KSO12. BUG=none TEST=Verified keyboard is functional with all keys detected BRANCH=none Change-Id: I1e3c1c2b6a4420cb6296b6bc921affa8c0ed5800 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/264610 Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r--chip/mec1322/keyboard_raw.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/chip/mec1322/keyboard_raw.c b/chip/mec1322/keyboard_raw.c
index da1b626db8..8569472682 100644
--- a/chip/mec1322/keyboard_raw.c
+++ b/chip/mec1322/keyboard_raw.c
@@ -47,11 +47,11 @@ test_mockable void keyboard_raw_drive_column(int out)
MEC1322_KS_KSO_SEL = 1 << 6; /* KSEN=1 */
gpio_set_level(GPIO_KBD_KSO2, 1);
} else {
- MEC1322_KS_KSO_SEL = out;
+ MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
gpio_set_level(GPIO_KBD_KSO2, 0);
}
#else
- MEC1322_KS_KSO_SEL = out;
+ MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE;
#endif
}
}