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| author | Gwendal Grignou <gwendal@chromium.org> | 2015-06-25 14:15:08 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-14 19:36:05 +0000 |
| commit | 7015336ea81aa1d57b62088a792d1c13cbc25d57 (patch) | |
| tree | b13c6543399c226e019f0c07a821cfadd5cccc93 /chip | |
| parent | ad099a3cf22a6441608b838cc3620fab527babba (diff) | |
| download | chrome-ec-7015336ea81aa1d57b62088a792d1c13cbc25d57.tar.gz | |
Ryu: i2c speed to 1MHz
To avoid FIFO errors - the fifo becomes full will we wait for the AP
to read the vectors, increase the i2c speed between EC and AP.
Target 1Mhz, 400KHz observed due to a limitation of the Tegra I2C
controller.
BRANCH=smaug
TEST=Verify with analyzer that speed is now 400KHz.
The duty cycle is still not right.
Check that FIFO underrun do not happen during tests.
BUG=chrome-os-partner:40280,chrome-os-partner:39233,chrome-os-partner:39900
Change-Id: Id6c2dfb10c34a919ec99a58bc0082207f7748b7e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284613
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/i2c-stm32f0.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c index dc9d295ae0..4d2da2a353 100644 --- a/chip/stm32/i2c-stm32f0.c +++ b/chip/stm32/i2c-stm32f0.c @@ -78,7 +78,7 @@ static void i2c_set_freq_port(const struct i2c_port_t *p) /* Set clock frequency */ switch (p->kbps) { case 1000: - STM32_I2C_TIMINGR(port) = 0x50110103; + STM32_I2C_TIMINGR(port) = 0x50100103; break; case 400: STM32_I2C_TIMINGR(port) = 0x50330309; |