diff options
| author | Dino Li <dino.li@ite.com.tw> | 2015-08-20 05:54:40 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-08-20 01:37:56 +0000 |
| commit | 911de4d175a2416370abc65b5dbc800a46c3fe3c (patch) | |
| tree | 0f3d45d185731df7da52f3b6ae4d9e06ca1a9c8b /chip | |
| parent | 8c633e5af603687d178047930dc502c7deefe0ae (diff) | |
| download | chrome-ec-911de4d175a2416370abc65b5dbc800a46c3fe3c.tar.gz | |
nds32: use INT_MASK instead of GIE
When there is an interrupt event, N8 CPU will save PSW register to IPSW
register and clear GIE then jump to interrupt service routine. N8 will
restore PSW from IPSW after "iret" instruction (the above are purely
hardware mechanism).
Nested interrupt will occur if we set GIE again in interrupt context.
symptom:
power button pressed while LID open -> exception or unknown reset.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Manually pressed power button x200.
2. Console "eflash" erase and write eflash OK.
Change-Id: Ic04a23d473ebc6417dffea814a27583cb8d63a1f
Reviewed-on: https://chromium-review.googlesource.com/289437
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/it83xx/flash.c | 12 | ||||
| -rw-r--r-- | chip/it83xx/gpio.c | 6 |
2 files changed, 6 insertions, 12 deletions
diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c index 9d2f7a7c39..5155e94332 100644 --- a/chip/it83xx/flash.c +++ b/chip/it83xx/flash.c @@ -347,7 +347,6 @@ int FLASH_DMA_CODE flash_physical_read(int offset, int size, char *data) */ int FLASH_DMA_CODE flash_physical_write(int offset, int size, const char *data) { - uint32_t psw = get_psw(); if (flash_dma_code_enabled == 0) return EC_ERROR_ACCESS_DENIED; @@ -367,8 +366,7 @@ int FLASH_DMA_CODE flash_physical_write(int offset, int size, const char *data) dma_flash_aai_write(offset, size, data); dma_reset_immu(); - if (psw & PSW_GIE) - interrupt_enable(); + interrupt_enable(); return dma_flash_verify(offset, size, data); } @@ -384,7 +382,6 @@ int FLASH_DMA_CODE flash_physical_write(int offset, int size, const char *data) int FLASH_DMA_CODE flash_physical_erase(int offset, int size) { int v_size = size, v_addr = offset; - uint32_t psw = get_psw(); if (flash_dma_code_enabled == 0) return EC_ERROR_ACCESS_DENIED; @@ -406,8 +403,7 @@ int FLASH_DMA_CODE flash_physical_erase(int offset, int size) } dma_reset_immu(); - if (psw & PSW_GIE) - interrupt_enable(); + interrupt_enable(); return dma_flash_verify(v_addr, v_size, NULL); } @@ -518,7 +514,6 @@ uint32_t flash_physical_get_writable_flags(uint32_t cur_flags) static void flash_code_static_dma(void) { - uint32_t psw = get_psw(); /* Make sure no interrupt while enable static DMA */ interrupt_disable(); @@ -548,8 +543,7 @@ static void flash_code_static_dma(void) flash_dma_code_enabled = 0x01; - if (psw & PSW_GIE) - interrupt_enable(); + interrupt_enable(); } /** diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c index 7ad348ce4b..f00c954f1c 100644 --- a/chip/it83xx/gpio.c +++ b/chip/it83xx/gpio.c @@ -440,9 +440,6 @@ static void __gpio_irq(void) } #endif - /* Run the GPIO master handler above with corresponding port/mask. */ - gpio_interrupt(gpio_irqs[irq].gpio_port, gpio_irqs[irq].gpio_mask); - /* * Clear the WUC status register. Note the external pin first goes * to the WUC module and is always edge triggered. @@ -454,6 +451,9 @@ static void __gpio_irq(void) * controller is level triggered from the WUC status. */ task_clear_pending_irq(irq); + + /* Run the GPIO master handler above with corresponding port/mask. */ + gpio_interrupt(gpio_irqs[irq].gpio_port, gpio_irqs[irq].gpio_mask); } /* Route all WKO interrupts coming from INT#2 into __gpio_irq. */ |