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authorShawn Nematbakhsh <shawnn@chromium.org>2015-11-02 09:05:04 -0800
committerchrome-bot <chrome-bot@chromium.org>2015-11-03 09:08:28 -0800
commit792d00184ab5f50af52b64e9c60cd01bc1b01fc7 (patch)
tree4ef540b64168f29419d4afb8021d5f1c93f3a482 /chip
parent37ff1d9696ecd8bcce67368ba4c40c8e17b55e7b (diff)
downloadchrome-ec-792d00184ab5f50af52b64e9c60cd01bc1b01fc7.tar.gz
stm32: i2c: Use correct timingr values based on clock source
Previous change 813e56e10af4 broke this by interchanging the values. BUG=chrome-os-partner:46188 BRANCH=None TEST=`make buildall -j` Change-Id: I9a66949b66e0d6736c007773740b4f7431faa3cc Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310057 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r--chip/stm32/i2c-stm32f0.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c
index 565006596f..4bc371a3dc 100644
--- a/chip/stm32/i2c-stm32f0.c
+++ b/chip/stm32/i2c-stm32f0.c
@@ -91,15 +91,15 @@ enum stm32_i2c_clk_src {
/* timingr register values for supported input clks / i2c clk rates */
static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = {
[I2C_CLK_SRC_48MHZ] = {
- [I2C_FREQ_1000KHZ] = 0x00100306,
- [I2C_FREQ_400KHZ] = 0x00310309,
- [I2C_FREQ_100KHZ] = 0x10420f13,
- },
- [I2C_CLK_SRC_8MHZ] = {
[I2C_FREQ_1000KHZ] = 0x50100103,
[I2C_FREQ_400KHZ] = 0x50330309,
[I2C_FREQ_100KHZ] = 0xB0421214,
},
+ [I2C_CLK_SRC_8MHZ] = {
+ [I2C_FREQ_1000KHZ] = 0x00100306,
+ [I2C_FREQ_400KHZ] = 0x00310309,
+ [I2C_FREQ_100KHZ] = 0x10420f13,
+ },
};
static void i2c_set_freq_port(const struct i2c_port_t *p,