diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-10-14 17:22:17 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-10-14 22:11:13 -0700 |
| commit | db77cafb3e254e95139949d5931554dd4a4d9f0c (patch) | |
| tree | 03c47b496ff1ee8afd2eb2fbc94ec28836eeee9b /chip | |
| parent | 3274fa21bb596dfc1a98c2a681a95c4a39c23cf6 (diff) | |
| download | chrome-ec-db77cafb3e254e95139949d5931554dd4a4d9f0c.tar.gz | |
stm32: i2c: Add timings for 8MHz i2cclk
Use the datasheet-specified 8MHz i2c timings, which are different from
the 48MHz timings.
BUG=chrome-os-partner:46188
BRANCH=None
TEST=Probe glados_pd i2c signals, verify that clock isn't stretched ~2us
on every bit received by slave.
Change-Id: Id6a07bc364163c2efc61c3115043f48a79027010
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/305714
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/i2c-stm32f0.c | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c index 8685ef5911..1c9ba7113b 100644 --- a/chip/stm32/i2c-stm32f0.c +++ b/chip/stm32/i2c-stm32f0.c @@ -69,6 +69,20 @@ static int wait_isr(int port, int mask) return EC_ERROR_TIMEOUT; } +#if defined(CONFIG_HOSTCMD_I2C_SLAVE_ADDR) && \ +defined(CONFIG_LOW_POWER_IDLE) && \ +(I2C_PORT_EC == STM32_I2C1_PORT) +/* 8MHz i2cclk register settings */ +#define STM32_I2C_TIMINGR_1000MHZ 0x00100306 +#define STM32_I2C_TIMINGR_400MHZ 0x00310309 +#define STM32_I2C_TIMINGR_100MHZ 0x10420f13 +#else +/* 48MHz i2cclk register settings */ +#define STM32_I2C_TIMINGR_1000MHZ 0x50100103 +#define STM32_I2C_TIMINGR_400MHZ 0x50330309 +#define STM32_I2C_TIMINGR_100MHZ 0xB0421214 +#endif + static void i2c_set_freq_port(const struct i2c_port_t *p) { int port = p->port; @@ -79,17 +93,17 @@ static void i2c_set_freq_port(const struct i2c_port_t *p) /* Set clock frequency */ switch (p->kbps) { case 1000: - STM32_I2C_TIMINGR(port) = 0x50100103; + STM32_I2C_TIMINGR(port) = STM32_I2C_TIMINGR_1000MHZ; break; case 400: - STM32_I2C_TIMINGR(port) = 0x50330309; + STM32_I2C_TIMINGR(port) = STM32_I2C_TIMINGR_400MHZ; break; case 100: - STM32_I2C_TIMINGR(port) = 0xB0421214; + STM32_I2C_TIMINGR(port) = STM32_I2C_TIMINGR_100MHZ; break; default: /* unknown speed, defaults to 100kBps */ CPRINTS("I2C bad speed %d kBps", p->kbps); - STM32_I2C_TIMINGR(port) = 0xB0421214; + STM32_I2C_TIMINGR(port) = STM32_I2C_TIMINGR_100MHZ; } /* Enable port */ STM32_I2C_CR1(port) = STM32_I2C_CR1_PE; |