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| author | CHLin <CHLIN56@nuvoton.com> | 2016-07-07 16:11:51 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-07-13 10:26:50 -0700 |
| commit | 3cb77ee041d3dbf9b27dc5baabcdf10b82914e48 (patch) | |
| tree | e0ccfe1a66083c5c919950dbf6775c7a24e0c4e1 /chip | |
| parent | 5c0ec1cab818582f8ecc4613e684172b1c1c62a5 (diff) | |
| download | chrome-ec-3cb77ee041d3dbf9b27dc5baabcdf10b82914e48.tar.gz | |
npcx: Clear IRQ11B bit when PM 1 is in enhanced mode
The bit IRQ11B of register HIIRQC is meaningful only when PM Channel 1
is in PC87570-Compatible. In previous commit, we deprecate use of
PC87570 mode but set the bit unintentionally. This will not cause any
bug but may make confused when reading the code.
Modified sources:
1. lpc.c: CLear IRQ11B in register HIIRQC.
BUG=chrome-os-partner:34346
TEST=make buildall -j; verify on Wheatley
BRANCH=none
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Change-Id: I594222c29557add847a1f689859fdf558d64fdd3
Reviewed-on: https://chromium-review.googlesource.com/358536
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/npcx/lpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index f1c0dbde33..a8a10d0a9a 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -851,7 +851,7 @@ static void lpc_init(void) */ NPCX_HIPMCTL(PMC_ACPI) |= 0x83; /* Normally Polarity IRQ1,12 type (level + high) setting */ - NPCX_HIIRQC = 0x04; + NPCX_HIIRQC = 0x00; /* * Init PORT80 |